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datasheet r01ds0248ej0110 rev.1.10 page 1 of 98 jan 13, 2016 rx23t group renesas mcus features 32-bit rx cpu core ? max. operating frequency: 40 mhz capable of 65.6 dmips in operation at 40 mhz ? enhanced dsp: 32-bit multi ply-accumulate and 16-bit multiply-subtract instructions supported ? built-in fpu: 32-bit single- precision floating point (compliant to ieee754) ? divider (fastest instruction ex ecution takes two cpu clock cycles) ? fast interrupt ? cisc harvard architecture with 5-stage pipeline ? variable-length instruct ions, ultra-compact code ? on-chip debugging circuit ? memory protection unit (mpu) supported low power design and architecture ? operation from a single 2.7-v to 5.5-v supply ? three low power consumption modes on-chip code flash memory, no wait states ? 128-/64-kbyte capacities ? on-board or off-board user programming on-chip sram, no wait states ? 12 kbytes of sram dma ? dtc: four transfer modes reset and supply management ? seven types of reset, includ ing the power-on reset (por) ? low voltage detection (lvd) with voltage settings clock functions ? main clock oscillator frequency: 1 to 20 mhz ? external clock input fre quency: up to 20 mhz ? pll circuit input: 4 mhz to 12.5 mhz ? on-chip low-speed oscilla tor, on-chip high-speed oscillator, dedica ted on-chip oscill ator for the iwdt ? clock frequency accuracy me asurement circuit (cac) independent watchdog timer ? 15-khz on-chip oscillator produces a dedicated clock signal to drive iwdt operation. useful functions for iec60730 compliance ? self-diagnostic and disconnection-dete ction assistance functions for the a/d convert er, clock frequency accuracy measurement circuit, inde pendent watchdog timer, ram test assistance functi ons using the doc, etc. mpc ? multiple locations are selectable for i/o pins of peripheral functions up to 4 communications channels ? sci with many useful f unctions (2 channels) asynchronous mode, clock sync hronous mode, smart card interface mode, simplified spi, simplified i 2 c, and extended serial mode. ? i 2 c bus interface: transfer at up to 400 kbps (one channel) ? rspi capable of high speed connection (one channel) up to 12 extended-function timers ? 16-bit mtu3: 40mhz operation, input capture, output compare, three-phase comp lementary pwm output, cpu- efficient complementary pwm, phase counting mode (six channels) ? 8-bit tmrs (4 channels), ? 16-bit compare-match timers (4 channels) 12-bit a/d converter: 10ch ? on-chip sample-and-hold circuit: 12bit up to 3 channels ? sampling time can be set for each channel ? self-diagnostic func tion and analog i nput disconnection detection assistance func tion (compliant to iec60730) ? adc: three sample-and-hol d circuits, double data registers, comparator (3 channels) register write protection function can protect values in important registers against overwriting. up to 50 pins for general i/o ports ? 5-v tolerant, open drain, input pull-up operating temperature range ?? 40 to +85 ?c ?? 40 to +105 ?c applications ? general industrial and consumer equipment PLQP0064KB-C 10 10 mm, 0.5 mm pitch plqp0052ja-b 10 10 mm, 0.65 mm pitch plqp0048kb-b 7 7 mm, 0.5 mm pitch 40-mhz 32-bit rx mcus, built-in fpu, 65.6 dmips, 12-bit adc (equipped with three s/h circuits, double data registers, and comparator) 40mhz pwm (three-phase complementary output 2ch) r01ds0248ej0110 rev.1.10 jan 13, 2016
r01ds0248ej0110 rev.1.10 page 2 of 98 jan 13, 2016 rx23t group 1. overview 1. overview 1.1 outline of specifications table 1.1 lists the specifications, and table 1.2 gives a comparison of the functions of the products in different packages. table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will differ in accordance with the p ackage type. for details, see table 1.2, comparison of functions for different packages . table 1.1 outline of specifications (1/3) classification module/function description cpu cpu ? maximum operating frequency: 40 mhz ? 32-bit rx cpu (rx v2) ? minimum instruction execution time: one instruction per clock cycle ? address space: 4-gbyte linear ? register set general purpose: sixteen 32-bit registers control: ten 32-bit registers accumulator: two 72-bit registers ? basic instructions: 75 variable-length instruction format ? floating-point instructions: 11 ? dsp instructions: 23 ? addressing modes: 11 ? data arrangement instructions: little endian data: selectable as little endian or big endian ? on-chip 32-bit multiplier: 32-bit 32-bit 64-bit ? on-chip divider: 32-bit 32-bit 32 bits ? barrel shifter: 32 bits ? memory protection unit (mpu) fpu ? single precision (32-bit) floating point ? data types and floating-point exceptions in conformance with the ieee754 standard memory rom ? capacity: 64 k/128 kbytes ? 32 mhz, no-wait memory access 32 to 40 mhz: wait states ? programming/erasing method: serial programming (asynchronous serial communication), self-programming ram ? capacity: 12 kbytes ? 40 mhz, no-wait memory access mcu operating mode single-chip mode clock clock generation circuit ? main clock oscillator, low-speed and high-speed on-chip oscillator, pll frequency synthesizer, and iwdt-dedicated on-chip oscillator ? oscillation stop detection: available ? clock frequency accuracy measurement circuit (cac): available ? independent settings for the system clock (iclk), peripheral module clock (pclk), and flashif clock (fclk) the cpu and system sections such as other bus masters run in synchronization with the system clock (iclk): 40 mhz (at max.) mtu3c runs in synchronization with the pclka: 40 mhz (at max.) peripheral modules other than mtu3c run in synchronization with the pclkb: 40 mhz (at max.) adclk operated in s12ade runs in synchronization with the pclkd: 40 mhz (at max.) the flash peripheral circuit runs in sync hronization with the fclk: 32 mhz (at max.) resets res# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and software reset voltage detection voltage detection circuit (lvdab) ? when the voltage on vcc falls below the voltage detection level, an internal reset or internal interrupt is generated. voltage detection circuit 0 is capable of selecting the detection voltage from 2 levels voltage detection circuit 1 is capable of selecting the detection voltage from 9 levels voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels low power consumption low power consumption functions ? module stop function ? three low power consumption modes sleep mode, deep sleep mode, and software standby mode function for lower operating power consumption ? operating power control modes high-speed operating mode and middle-speed operating mode
r01ds0248ej0110 rev.1.10 page 3 of 98 jan 13, 2016 rx23t group 1. overview interrupt interrupt controller (icub) ? interrupt vectors: 83 ? external interrupts: 7 (nmi, irq0 to irq5 pins) ? non-maskable interrupts: 5 (nmi pin, oscillation stop detection interrupt, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt, and iwdt interrupt) ? 16 levels specifiable for the order of priority dma data transfer controller (dtca) ? transfer modes: normal transfer, repeat transfer, and block transfer ? activation sources: interrupts ? chain transfer function i/o ports general i/o ports 64-/52-/48-pin ? i/o: 50/40/37 ? input: 1/1/1 ? pull-up resistors: 50/40/37 ? open-drain outputs: 42/32/29 ? 5-v tolerance: 2/2/2 multi-function pin controller (mpc) capable of selecting the input/output function from multiple pins timers multi-function timer pulse unit 3 (mtu3c) ? 6 units (16bis 6 channels) ? provides up to 16 pulse-input/output lines and three pulse-input lines ? select from among fourteen counter-input clock si gnals for each channel (pclk/1, pclk/2, pclk/4, pclk/8, pclk/16, pclk/32, pclk/64, pclk /256, pclk/1024, mtclka, mtclkb, mtclkc, mtclkd, mtioc1a) other than channel 1/3/4, for whic h only eleven signals are available, channel 2 for 12, channel 5 for 10 ? 26 output compare/input capture registers ? counter clear operation (with compare match- or input capture-sourced simultaneous counter clear capability) ? simultaneous writing to multiple timer counters (tcnt) ? simultaneous register input/output by synchronous counter operation ? buffer operation ? cascaded operation ? 28 interrupt sources ? automatic transfer of register data ? pulse output modes: toggle/pwm/complementary pwm/reset-synchronized pwm ? complementary pwm output mode 3-phase non-overlapping waveform output for inverter control automatic dead time setting adjustable pwm duty cycle: from 0 to 100% a/d conversion request delaying function interrupt at crest/trough can be skipped double buffer function ? reset-synchronized pwm mode outputs three phases each for positive and negative pwm waveforms in user-specified duty cycle ? phase counting modes: 16-bit mode (channel 1 and 2)/32-bit mode (channel 1 and 2) ? dead time compensation counter function ? a/d converter start trigger can be generated ? a/d converter start triggers can be skipped ? signals from the input capture and external c ounter clock pins are input via a digital filter port output enable 3 (poe3b) controls the high-impedance state of the mtu?s waveform output pins compare match timer (cmt) ? (16 bits 2 channels) 2 units ? select from among four clock signals (pclk/8, pclk/32, pclk/128, pclk/512) independent watchdog timer (iwdta) ? 14 bits 1 channel ? count clock: dedicated low-speed on-chip oscillator for the iwdt frequency divided by 1, 16, 32, 64, 128, or 256 8-bit timer (tmr) ? (8 bits 2 channels) 2 units ? s even internal clocks (pclk/1, pclk/2, pclk/8, pclk/32, pclk/ 64, pclk/1024, and pclk/8192) and an external clock can be selected ? pulse output and pwm output with any duty cycle are available ? two channels can be cascaded and used as a 16-bit timer ? generates a/d conversion start trigger ? generates baud rate clock for the sci5 table 1.1 outline of specifications (2/3) classification module/function description
r01ds0248ej0110 rev.1.10 page 4 of 98 jan 13, 2016 rx23t group 1. overview communication functions serial communications interfaces (scig) ? 2 channels (channel 1 and 5: scig) ? scig serial communications modes: asynchronous, clock synchronous, and smart-card interface on-chip baud rate generator allows selection of the desired bit rate choice of lsb-first or msb-first transfer average transfer rate clock can be input from tmr timers for sci5 simple i 2 c simple spi 9-bit transfer mode bit rate modulation i 2 c bus interface (riica) ? 1 channel ? communications formats: i 2 c bus format/smbus format ? master mode or slave mode selectable ? supports fast mode serial peripheral interface (rspia) ? 1 channel ? transfer facility using the mosi (master out, slave in), miso (mast er in, slave out), ssl (slave select), and rspi clock (rspck) signals enables serial transfer through spi operation (four lines) or clock- synchronous operation (three lines) ? capable of handling serial transfer as a master or slave ? data formats ? choice of lsb-first or msb-first transfer the number of bits in each transfer can be changed to 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or 32 bits. 128-bit buffers for transmission and reception up to four frames can be transmitted or receiv ed in a single transfer operation (with each frame having up to 32 bits) ? double buffers for both transmission and reception 12-bit a/d converter (s12ade) ? 12 bits (10 channels 1 unit) ? 12-bit resolution ? minimum conversion time: 1.0 s per channel when the adclk is operating at 40 mhz ? operating modes scan mode (single scan mode, continuous scan mode, and group scan mode) group a priority control (only for group scan mode) ? sampling variable sampling time can be set up for each channel ? self-diagnostic function ? double trigger mode (a/d conversion data duplicated) ? detection of analog input disconnection ? a/d conversion start conditions a software trigger, a trigger from a timer (mtu, tmr), or an external trigger signal comparator c (cmpc) ? 3 channels ? function to compare the reference voltage and the analog input voltage ? reference voltage: select from among two voltages ? analog input voltage: select from among four voltages d/a converter (da) for generating comparator c reference voltage ? 1 channel ? 8-bit resolution ? output voltage: 0 to avcc0 ? reference voltage generation circuit for comparator c crc calculator (crc) ? crc code generation for arbitrary amounts of data in 8-bit units ? select any of three generating polynomials: x 8 + x 2 + x + 1, x 16 + x 15 + x 2 + 1, or x 16 + x 12 + x 5 + 1 ? generation of crc codes for use with lsb-firs t or msb-first communications is selectable. data operation circuit (doc) comparison, addition, and subtraction of 16-bit data power supply voltages/operating frequencies vcc = 2.7 to 5.5v: 40mhz supply current 15 ma at 40 mhz (typ.) operating temperature range d version: ? 40 to +85c, g version: ? 40 to +105c packages 64-pin lfqfp 0.5mm pitch 52-pin lqfp 0.65mm pitch 48-pin lfqfp 0.5mm pitch on-chip debugging system e1 emulator (fine interface) table 1.1 outline of specifications (3/3) classification module/function description
r01ds0248ej0110 rev.1.10 page 5 of 98 jan 13, 2016 rx23t group 1. overview note 1. for multi-function timer pulse unit 3, the number of pi ns differs depending on the package. for details, see the "list o f pins and pin functions" table for each pin. table 1.2 comparison of functions for different packages module/functions rx23t group 48 pins 52 pins 64 pins interrupts external interrupts nmi, irq0 to irq5 dtc data transfer controller available timers multi-function timer pulse unit 3* 1 6 channels port output enable 3 poe0# to poe8#, poe10# 8-bit timer 2 channels 2 units compare match timer 2 channels 2 units independent watchdog timer available communication functions serial communications interfaces (scig) [including simple iic and simple spi] 2 channels (sci1, 5) i 2 c bus interface 1 channel serial peripheral interface 1 channel 12-bit a/d converter (including high-precision channels) 10 channels (8 channels) crc calculator available packages 48-pin lfqfp 52-pin lqfp 64-pin lfqfp
r01ds0248ej0110 rev.1.10 page 6 of 98 jan 13, 2016 rx23t group 1. overview 1.2 list of products table 1.3 and table 1.4 are a list of products, and figure 1.1 shows how to read the product part no., memory capacity, and package type. table 1.3 list of products: d version (t a = ?40 to +85c) group part no. package rom capacity ram capacity operating frequency operating temperature rx23t r5f523t5adfl plqp0048kb-b 128 kbytes 12 kbytes 40mhz -40 to + 85c r5f523t5adfd plqp0052ja-b r5f523t5adfm PLQP0064KB-C r5f523t3adfl plqp0048kb-b 64 kbytes r5f523t3adfd plqp0052ja-b r5f523t3adfm PLQP0064KB-C table 1.4 list of products: g version (t a = ?40 to +105c) group part no. package rom capacity ram capacity operating frequency operating temperature rx23t r5f523t5agfl plqp0048kb-b 128 kbytes 12 kbytes 40mhz -40 to +105c r5f523t5agfd plqp0052ja-b r5f523t5agfm PLQP0064KB-C r5f523t3agfl plqp0048kb-b 64 kbytes r5f523t3agfd plqp0052ja-b r5f523t3agfm PLQP0064KB-C
r01ds0248ej0110 rev.1.10 page 7 of 98 jan 13, 2016 rx23t group 1. overview figure 1.1 how to read the product part number type of memory f: flash memory version package type, number of pins, and pin pitch fm: lfqfp/64/0.50 fd: lqfp/52/0.65 fl: lfqfp/48/0.50 rom/ram capacity 5: 128 kbytes/12 kbytes 3: 64 kbytes/12 kbytes group name 3t: rx23t group renesas mcu renesas semiconductor product series name rx200 series r 5 f 5 2 d f m a5t3 d: operating peripheral te mperature: ?40 to +85c g: operating peripheral temperature: ?40 to +105c a: 5v
r01ds0248ej0110 rev.1.10 page 8 of 98 jan 13, 2016 rx23t group 1. overview 1.3 block diagram figure 1.2 shows a block diagram. figure 1.2 block diagram 12-bit a/d converter 10 channels mtu3c 6ch cmt 2 channels (unit 0) poe3b tmr 2 channels (unit 0) tmr 2 channels (unit 1) cmt 2 channels (unit 1) riica 1ch rspia 1ch scig 2ch crc iwdta clock generation circuit rx cpu ram rom doc dtca icub cac comparator c 3 channels mpu operand bus instruction bus internal main bus 1 internal main bus 2 internal peripheral buses 1 to 6 port d port e port a port b port 9 port 7 port 0 port 1 port 3 port 4 port 2 icub: interrupt controller dtca: data transfer controller iwdta: independent watchdog timer crc: crc (cyclic redundanc y check) calculator scig: serial communications interface rspia: serial peripheral interface riica i 2 c bus interface mtu3c multi-function timer pulse unit 3 poe3b port output enable 3 cmt compare match timer doc data operation circuit cac clock frequency accuracy measurement circuit mpu memory protection unit tmr 8-bit timer
r01ds0248ej0110 rev.1.10 page 9 of 98 jan 13, 2016 rx23t group 1. overview 1.4 pin functions table 1.5 lists the pin functions. table 1.5 pin functions (1/2) classifications pin name i/o description power supply vcc input power supply pin. connect it to the system power supply. vcl ? connect this pin to the vss pin via the 4.7 f smoothing capacitor used to stabilize the internal power supply. pl ace the capacitor close to the pin. vss input ground pin. connect it to the system power supply (0 v). clock xtal output pins for connecting a crystal. an external clock can be input through the extal pin. extal input operating mode control md input pin for setting the operating mode. the signal levels on this pin must not be changed during operation. system control res# input reset pin. this mcu enters the reset state when this signal goes low. cac cacref input input pin for the clock fr equency accuracy m easurement circuit. on-chip emulator fined i/o fine interface pin. interrupts nmi input non-maskable interrupt request pin. irq0 to irq5 input interrupt request pins. multi-function timer pulse unit 3 mtioc0a, mtioc0b mtioc0c, mtioc0d i/o the tgra0 to tgrd0 input capture input/output compare output/pwm output pins. mtioc1a, mtioc1b i/o the tgra1 and tgrb1 input capture input/output compare output/pwm output pins. mtioc2a, mtioc2b i/o the tgra2 and tgrb2 input capture input/output compare output/pwm output pins. mtioc3a, mtioc3b mtioc3c, mtioc3d i/o the tgra3 to tgrd3 input capture input/output compare output/pwm output pins. mtioc4a, mtioc4b mtioc4c, mtioc4d i/o the tgra4 to tgrd4 input capture input/output compare output/pwm output pins. mtic5u, mtic5v, mtic5w input the tgru5, tgrv5, and tgrw5 input capture input/external pulse input pins. mtclka, mtclkb, mtclkc, mtclkd input input pins for the external clock. adsm0 output a/d trigger output pin. port output enable 3 poe0#, poe8#, poe10# input input pins for request signals to place the mtu pins in the high impedance state. 8-bit timer tmo0 to tmo3 output compare match output pins. tmci0 to tmci3 input input pins for the external clock to be input to the counter. tmri0 to tmri3 input counter reset input pins. serial communications interface (scig) ? asynchronous mode/clock synchronous mode sck1, sck5 i/o input/output pins for the clock. rxd1, rxd5 input input pins for received data. txd1, txd5 output output pins for transmitted data. cts1#, cts5# input input pins for controllin g the start of transmission and reception. rts1#, rts5# output output pins for contro lling the start of transmission and reception. ? simple i 2 c mode sscl1, sscl5 i/o input/output pins for the i 2 c clock. ssda1, ssda5 i/o input/output pins for the i 2 c data.
r01ds0248ej0110 rev.1.10 page 10 of 98 jan 13, 2016 rx23t group 1. overview serial communications interface (scig) ? simple spi mode sck1, sck5 i/o input/output pins for the clock. smiso1, smiso5 i/o input/output pins for slave transmit data. smosi1, smosi5 i/o input/output pins for master transmit data. ss1#, ss5# input chip-select input pins. i 2 c bus interface scl0 i/o input/output pin for i 2 c bus interface clocks. bus can be directly driven by the n-channel open drain output. sda0 i/o input/output pin for i 2 c bus interface data. bus can be directly driven by the n-channel open drain output. serial peripheral interface rspcka i/o input/output pin for the rspi clock. mosia i/o input/output pin for transmitting data from the rspi master. misoa i/o input/output pin for transmitting data from the rspi slave. ssla0 i/o input/output pin to select the slave for the rspi. ssla1 to ssla3 output output pins to select the slave for the rspi. 12-bit a/d converter an000 to an007, an016, an017 input input pins for the analog signals to be processed by the a/d converter. adtrg0# input input pin for the external tri gger signals that start the a/d conversion. adst0 output output pin for a/d conversion status. comparator c cmpc00, cmpc01, cmpc02 input analog input pin for cmpc0 cmpc10, cmpc11, cmpc12 input analog input pin for cmpc1 cmpc20, cmpc21, cmpc22 input analog input pin for cmpc2 comp0 to comp2 output comparator detection result output pins. cvrefc0, cvrefc1 input analog reference voltage supply pins for comparator c. analog power supply avcc0 input analog voltage supply pin for the 12-bit a/d converter, comparator c, and the 8-bit d/a converter for generating comparator c reference voltage. connect this pin to vcc when these modules are not used. avss0 input analog ground pin for the 12-bit a/d converter, comparator c, and the 8- bit d/a converter for generating comparator c reference voltage. connect this pin to vss when these modules are not used. vrefh0 input analog reference voltage supply pin for the 12-bit a/d converter. vrefl0 input analog reference ground pin for the 12-bit a/d converter. i/o ports p00 to p02 i/o 3-bit input/output pins. p10, p11 i/o 2-bit input/output pins. p22 to p24 i/o 3-bit input/output pins. p30 to p33, p36, p37 i/o 6-bit input/output pins. p40 to p47 i/o 8-bit input/output pins. p70 to p76 i/o 7-bit input/output pins. p91 to p94 i/o 4-bit input/output pins. pa2 to pa5 i/o 4-bit input/output pins. pb0 to pb7 i/o 8-bit input/output pins. pd3 to pd7 i/o 5-bit input/output pins. pe2 input 1-bit input pin. table 1.5 pin functions (2/2) classifications pin name i/o description
r01ds0248ej0110 rev.1.10 page 11 of 98 jan 13, 2016 rx23t group 1. overview 1.5 pin assignments figure 1.3 to figure 1.5 show the pin assignments. table 1.6 to table 1.8 show the lists of pins and pin functions. figure 1.3 pin assignments of the 64-pin lfqfp 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 54 55 51 49 50 52 53 56 57 58 59 60 61 63 64 62 rx23t group PLQP0064KB-C (64-pin lfqfp) (upper perspective view) p47 p46 p45 p44 p43 p42 p41 p40 avcc0 vrefh0 vrefl0 avss0 p11 p10 pa5 pa4 p22 p23 p24 p30 vss p31 vcc p32 p33 p70 p71 p72 p73 p74 p75 p76 p91 p92 p93 p94 pa2 pa3 pb0 pb1 pb2 pb3 vss pb4 vcc pb5 pb6 pb7 p02 p00 vcl p01 md res# p37/xtal vss p36/extal vcc pe2 pd7 pd6 pd5 pd4 pd3 this figure indicates the power supply pins and i/o port pins. for the pin configuration, see the table ?list of pins and pin functions (64-pin lfqfp)?. note:
r01ds0248ej0110 rev.1.10 page 12 of 98 jan 13, 2016 rx23t group 1. overview figure 1.4 pin assignments of the 52-pin lqfp this figure indicates the power supply pins and i/o port pins. for the pin configuration, see the table ?list of pins and pin functions (52-pin lqfp)?. 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 1 2 3 4 5 6 7 8 9 10 11 12 13 42 43 40 41 44 45 46 47 48 49 51 52 50 rx23t group plqp0052ja-b (52-pin lqfp) (upper perspective view) p47 p46 p45 p44 p43 p42 p41 p40 avcc0 avss0 p11 p10 pa5 p22 p23 p24 vss vcc p33 p70 p71 p72 p73 p74 p75 p76 p93 p94 pa2 pa3 pb0 pb1 pb2 pb3 pb4 vcc pb5 pb6 pb7 p02 vcl md res# p37/xtal vss p36/extal vcc pe2 pd6 pd5 pd4 pd3 note:
r01ds0248ej0110 rev.1.10 page 13 of 98 jan 13, 2016 rx23t group 1. overview figure 1.5 pin assignments of the 48-pin lfqfp this figure indicates the power supply pins and i/o port pins. for the pin configuration, see the table ?list of pins and pin functions (48-pin lfqfp)?. 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12 38 39 37 40 41 42 43 44 45 47 48 46 rx23t group plqp0048kb-b (48-pin lfqfp) (upper perspective view) p47 p46 p45 p44 p43 p42 p41 p40 avcc0 avss0 p11 p10 p22 p23 p24 vss vcc p70 p71 p72 p73 p74 p75 p76 p93 p94 pa2 pa3 pb0 pb1 pb2 pb3 pb4 vcc pb5 pb6 vcl md res# p37/xtal vss p36/extal vcc pe2 pd6 pd5 pd4 pd3 18 17 16 15 14 13 note:
r01ds0248ej0110 rev.1.10 page 14 of 98 jan 13, 2016 rx23t group 1. overview table 1.6 list of pins and pin functions (64-pin lfqfp) (1/2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe, cac) communications (scig, rspi, riic) others 1 p02 cts1#/rts1#/ss1# adst0/irq5 2p00 irq2 3vcl 4 p01 cacref irq4 5md fined 6 res# 7xtal p37 8 vss 9 extal p36 10 vcc 11 pe2 poe10# nmi 12 pd7 tmri1 ssla1 13 pd6 tmo1 ssla0/cts1#/rts1#/ss1# adst0/irq5 14 pd5 tmri0 rxd1/smiso1/sscl1 irq3 15 pd4 tmci0 sck1 irq2 16 pd3 tmo0 txd1/smosi1/ssda1 17 pb7 sck5 18 pb6 rxd5/smiso5/sscl5 irq5 19 pb5 txd5/smosi5/ssda5 20 vcc 21 pb4 poe8# irq3 22 vss 23 pb3 mtioc0a/cacref sck5/rspcka 24 pb2 mtioc0b/adsm0 txd5/smosi5/ssda5/sda0 25 pb1 mtioc0c rxd5/smiso5/sscl5/scl0 irq2 26 pb0 mtioc0d mosia 27 pa3 mtioc2a ssla0 28 pa2 mtioc2b cts5#/rts5#/ss5#/ssla1 irq4 29 p94 mtioc0c/tmo1 misoa irq1 30 p93 mtioc0b/tmri1 sck5/rspcka irq0 31 p92 tmci1 ssla2 32 p91 ssla3 33 p76 mtioc4d 34 p75 mtioc4c 35 p74 mtioc3d 36 p73 mtioc4b 37 p72 mtioc4a 38 p71 mtioc3b 39 p70 poe0# irq5 40 p33 mtioc3a/mtclka ssla3 41 p32 mtioc3c/mtclkb ssla2 42 vcc 43 p31 mtioc0a/mtclkc ssla1 44 vss 45 p30 mtioc0b/mtclkd ssla0 46 p24 mtic5u/tmci2 rspcka comp0/irq3 47 p23 mtic5v/cacref/tmo2 mosia comp1/irq4 48 p22 mtic5w/tmri2 misoa comp2/irq2 49 p47 an007/cmpc12/ cmpc22 50 p46 an006/cmpc02 51 p45 an005/cmpc21 52 p44 an004/cmpc11 53 p43 an003/cmpc01
r01ds0248ej0110 rev.1.10 page 15 of 98 jan 13, 2016 rx23t group 1. overview 54 p42 an002/cmpc20 55 p41 an001/cmpc10 56 p40 an000/cmpc00 57 avcc0 58 vrefh0 59 vrefl0 60 avss0 61 p11 mtioc3a/mtclkc/tmo3 irq1/an016/ cvrefc0 62 p10 mtclkd/tmri3 irq0/an017/ cvrefc1 63 pa5 mtioc1a/tmci3 misoa 64 pa4 mtioc1b rspcka adtrg0# table 1.6 list of pins and pin functions (64-pin lfqfp) (2/2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe, cac) communications (scig, rspi, riic) others
r01ds0248ej0110 rev.1.10 page 16 of 98 jan 13, 2016 rx23t group 1. overview table 1.7 list of pins and pin functions (52-pin lqfp) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe, cac) communications (scig, rspi, riic) others 1 p02 cts1#/rts1#/ss1# adst0/irq5 2vcl 3md fined 4 res# 5xtal p37 6 vss 7 extal p36 8vcc 9 pe2 poe10# nmi 10 pd6 tmo1 ssla0/cts1#/rts1#/ss1# adst0/irq5 11 pd5 tmri0 rxd1/smiso1/sscl1 irq3 12 pd4 tmci0 sck1 irq2 13 pd3 tmo0 txd1/smosi1/ssda1 14 pb7 sck5 15 pb6 rxd5/smiso5/sscl5 irq5 16 pb5 txd5/smosi5/ssda5 17 vcc 18 pb4 poe8# irq3 19 pb3 mtioc0a/cacref sck5/rspcka 20 pb2 mtioc0b/adsm0 txd5/smosi5/ssda5/sda0 21 pb1 mtioc0c rxd5/smiso5/sscl5/scl0 irq2 22 pb0 mtioc0d mosia 23 pa3 mtioc2a ssla0 24 pa2 mtioc2b cts5#/rts5#/ss5#/ssla1 irq4 25 p94 mtioc0c/tmo1 misoa irq1 26 p93 mtioc0b/tmri1 sck5/rspcka irq0 27 p76 mtioc4d 28 p75 mtioc4c 29 p74 mtioc3d 30 p73 mtioc4b 31 p72 mtioc4a 32 p71 mtioc3b 33 p70 poe0# irq5 34 p33 mtioc3a/mtclka ssla3 35 vcc 36 vss 37 p24 mtic5u/tmci2 rspcka comp0/irq3 38 p23 mtic5v/cacref/tmo2 mosia comp1/irq4 39 p22 mtic5w/tmri2 misoa comp2/irq2 40 p47 an007/cmpc12/ cmpc22 41 p46 an006/cmpc02 42 p45 an005/cmpc21 43 p44 an004/cmpc11 44 p43 an003/cmpc01 45 p42 an002/cmpc20 46 p41 an001/cmpc10 47 p40 an000/cmpc00 48 avcc0 49 avss0 50 p11 mtioc3a/mtclkc/tmo3 irq1/an016/ cvrefc0 51 p10 mtclkd/tmri3 irq0/an017/ cvrefc1 52 pa5 mtioc1a/tmci3 misoa
r01ds0248ej0110 rev.1.10 page 17 of 98 jan 13, 2016 rx23t group 1. overview table 1.8 list of pins and pin functions (48-pin lfqfp) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe, cac) communications (scig, rspi, riic) others 1vcl 2md fined 3 res# 4xtal p37 5 vss 6 extal p36 7vcc 8 pe2 poe10# nmi 9 pd6 tmo1 ssla0/cts1#/rts1#/ss1# adst0/irq5 10 pd5 tmri0 rxd1/smiso1/sscl1 irq3 11 pd4 tmci0 sck1 irq2 12 pd3 tmo0 txd1/smosi1/ssda1 13 pb6 rxd5/smiso5/sscl5 irq5 14 pb5 txd5/smosi5/ssda5 15 vcc 16 pb4 poe8# irq3 17 pb3 mtioc0a/cacref sck5/rspcka 18 pb2 mtioc0b/adsm0 txd5/smosi5/ssda5/sda0 19 pb1 mtioc0c rxd5/smiso5/sscl5/scl0 irq2 20 pb0 mtioc0d mosia 21 pa3 mtioc2a ssla0 22 pa2 mtioc2b cts5#/rts5#/ss5#/ssla1 irq4 23 p94 mtioc0c/tmo1 misoa irq1 24 p93 mtioc0b/tmri1 sck5/rspcka irq0 25 p76 mtioc4d 26 p75 mtioc4c 27 p74 mtioc3d 28 p73 mtioc4b 29 p72 mtioc4a 30 p71 mtioc3b 31 p70 poe0# irq5 32 vcc 33 vss 34 p24 mtic5u/tmci2 rspcka comp0/irq3 35 p23 mtic5v/cacref/tmo2 mosia comp1/irq4 36 p22 mtic5w/tmri2 misoa comp2/irq2 37 p47 an007/cmpc12/ cmpc22 38 p46 an006/cmpc02 39 p45 an005/cmpc21 40 p44 an004/cmpc11 41 p43 an003/cmpc01 42 p42 an002/cmpc20 43 p41 an001/cmpc10 44 p40 an000/cmpc00 45 avcc0 46 avss0 47 p11 mtioc3a/mtclkc/tmo3 irq1/an016/ cvrefc0 48 p10 mtclkd/tmri3 irq0/an017/ cvrefc1
r01ds0248ej0110 rev.1.10 page 18 of 98 jan 13, 2016 rx23t group 2. cpu 2. cpu figure 2.1 shows register set of the cpu. figure 2.1 register set of the cpu note 1. the stack pointer (sp) can be the interrupt stack pointer (isp) or user stack pointer (usp), according to the value of the u bit in the psw. r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 (sp) *1 general-purpose register b31 b0 dsp instruction register b71 b0 acc0 (accumulator 0) acc1 (accumulator 1) usp (user stack pointer) isp (interrupt stack pointer) intb (interrupt table register) pc (program counter) psw (processor status word) bpc (backup pc) bpsw (backup psw) fintv (fast interrupt vector register) fpsw (floating-point status word) control register b31 b0 extb (exception table register)
r01ds0248ej0110 rev.1.10 page 19 of 98 jan 13, 2016 rx23t group 2. cpu 2.1 general-purpose r egisters (r0 to r15) this cpu has sixteen 32-bit general-purpose registers (r0 to r15). r0 to r15 can be used as data registers or address registers. r0, a general-purpose register, also functions as the stack pointer (sp). the stack pointer is switched to operate as the interrupt stack pointer (isp) or user stack pointer (usp) by the value of the stack pointer select bit (u) in the processor status word (psw). 2.2 control registers (1) interrupt stack pointer (isp) and user stack pointer (usp) the stack pointer (sp) can be either of two types, the interrupt stack point er (isp) or the user stack pointer (usp). whether the stack pointer operates as the isp or usp depends on the value of the stack poi nter select bit (u) in the processor status word (psw). set the isp or usp to a multiple of 4 to reduce the number of cycles required to execute interrupt sequences and instructions entailing stack manipulation. (2) exception table register (extb) the exception table register (extb) specifies the address wher e the exception vector table starts. set the extb to a multiple of 4 to reduce the number of cycles required to execute interrupt sequences and instructions entailing stack manipulation. (3) interrupt table register (intb) the interrupt table register (int b) specifies the address where th e interrupt vector table starts. set the intb to a multiple of 4 to reduce the number of cycl es required to execute interr upt sequences and instructions entailing stack manipulation. (4) program counter (pc) the program counter (pc) indicates the a ddress of the instruction being executed. (5) processor status word (psw) the processor status word (psw) i ndicates the results of instruction execution or the state of the cpu. (6) backup pc (bpc) the backup pc (bpc) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the program counter (pc) are saved in the bpc register. (7) backup psw (bpsw) the backup psw (bpsw) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the processor status word (psw ) are saved in the bpsw. the allocation of bits in the bpsw corresponds to that in the psw. (8) fast interrupt vector register (fintv) the fast interrupt vector register (fintv) is provided to speed up response to interrupts. the fintv register specifies a bran ch destination address when a fa st interrupt has been generated.
r01ds0248ej0110 rev.1.10 page 20 of 98 jan 13, 2016 rx23t group 2. cpu (9) floating-point st atus word (fpsw) the floating-point status word (fpsw) indicates the results of floating-point operations. when an exception handling enable bit (e j) enables the exception handling (ej = 1) , the exception cause can be identified by checking the corresponding cj flag in the exception handling routine. if th e exception handling is masked (ej = 0), the occurrence of exception can be ch ecked by reading the fj flag at the end of a series of pro cessing. once the fj flag has been set to 1, this value is retained until it is cleared to 0 by software (j = x, u, z, o, or v). 2.3 accumulator the accumulator (acc0 or acc1) is a 72-bit register used for dsp instruct ions. the accumulator is handled as a 96-bit register for reading and writing. at this time, when bits 95 to 72 of the accumulator are read , the value where the value of bit 71 is sign extended is read . writing to bits 95 to 72 of the accumulator is ignored. acc0 is also used for the multiply and multiply-and-accumulate in structions; emul, emulu, fmul, mul, and rmpa, in whic h case the prior value in acc0 is modified by execu tion of the instruction. use the mvtacgu, mvtachi, and mvtaclo instructi ons for writing to the accu mulator. the mvtacgu, mvtachi, and mvtaclo instructions write data to bits 95 to 64, the higher-order 32 bits (bits 63 to 32), and the lower-order 32 bits (bits 31 to 0), respectively. use the mvfacgu, mvfa chi, mvfacmi, and mvfaclo in structions for reading data from the accumulator. the mvfacgu, mvfachi, mvfacmi, and mvfaclo instructions r ead data from the guard bits (bits 95 to 64), higher- order 32 bits (bits 63 to 32), the middle 32 bits (bits 47 to 16), and the lower-order 32 bits (bits 31 to 0), respectively.
r01ds0248ej0110 rev.1.10 page 21 of 98 jan 13, 2016 rx23t group 3. address space 3. address space 3.1 address space this lsi has a 4-gbyte address space, consisting of the rang e of addresses from 0000 0000 h to ffff ffffh. that is, linear access to an address space of up to 4 gbytes is po ssible, and this contains bo th program and data areas. figure 3.1 shows the memory maps in the re spective operating modes. accessible areas will differ according to the operating mode and states of control bits.
r01ds0248ej0110 rev.1.10 page 22 of 98 jan 13, 2016 rx23t group 3. address space figure 3.1 memory map in each operating mode reserved area *3 reserved area *3 reserved area *3 reserved area *3 0000 0000h 0008 0000h ffff ffffh single-chip mode *1 ram *2 on-chip rom (program rom) (read only) *2 0010 0000h peripheral i/o registers 0080 0000h fffe 0000h peripheral i/o registers peripheral i/o registers 007f c000h 007f c500h 007f fc00h 0000 2800h ram *2 0000 4000h 0008 4a80h reserved area *3 note 1. the address space in boot mode is the sa me as the address space in single-chip mode. note 2. the capacity of rom/ram differs depending on the products. note: see table 1.3 and table 1.4 list of products, for the product type name. note 3. reserved areas should not be accessed. rom (bytes) ram (bytes) capacity address capacity address 128 kbytes fffe 0000h to ffff ffffh 12 kbytes 0000 0000h to 0000 27ffh 0000 4000h to 0000 4a7fh 64 kbytes ffff 0000h to ffff ffffh
r01ds0248ej0110 rev.1.10 page 23 of 98 jan 13, 2016 rx23t group 4. i/o registers 4. i/o registers this section provides information on the on-chip i/o register addresses and bit configuration. the information is given as shown below. notes on writing to registers are also given below. (1) i/o register addresses (address order) ? registers are listed from th e lower allocation addresses. ? registers are classified acco rding to module symbols. ? numbers of cycles for access indicate numbers of cycles of the given base clock. ? among the internal i/o register area, a ddresses not listed in the list of regi sters are reserved. reserved addresses must not be accessed. do not access these addresses; ot herwise, the operation when accessing these bits and subsequent operations cannot be guaranteed. (2) notes on writing to i/o registers when writing to an i/o register , the cpu starts executing the subsequent instru ction before completing i/o register write. this may cause the subsequent instruction to be executed befo re the post-update i/o register value is reflected on the operation. as described in the following examples, sp ecial care is required for the cases in wh ich the subsequent instruction must be executed after the post-update i/o re gister value is actually reflected. [examples of cases requiring special care] ? the subsequent instruction must be execu ted while an interrupt request is disabled with the ienj bit in iern of the icu (interrupt request en able bit) cleared to 0. ? a wait instruction is executed immediately after the preprocessing for causing a transition to the low power consumption state. in the above cases, after writing to an i/o register, wait until the write operation is completed using the following procedure and then execute the subsequent instruction. (a) write to an i/o register. (b) read the value from the i/o re gister to a general register. (c) execute the operati on using the value read. (d) execute the subsequent instruction. [instruction examples] ? byte-size i/o registers mov.l #sfr_addr, r1 mov.b #sfr_data, [r1] cmp [r1].ub, r1 ;; next process ? word-size i/o registers mov.l #sfr_addr, r1 mov.w #sfr_data, [r1] cmp [r1].w, r1 ;; next process
r01ds0248ej0110 rev.1.10 page 24 of 98 jan 13, 2016 rx23t group 4. i/o registers ? longword-size i/o registers mov.l #sfr_addr, r1 mov.l #sfr_data, [r1] cmp [r1].l, r1 ;; next process if multiple registers are written to and a subsequent instruc tion should be executed after th e write operati ons are entirely completed, only read the i/o register that was last written to and execute the operation using th e value; it is not necessary to read or execute operation for all the registers that were written to. (3) number of access cycles to i/o registers for numbers of clock cycles fo r access to i/o registers, see table 4.1, list of i/o registers (address order) . the number of access cycles to i/o regist ers is obtained by following equation. * 1 number of access cycles to i/o registers = numb er of bus cycles for internal main bus 1 + number of divided clock synchronization cycles + number of bus cycles for internal peripheral bus 1 to 6 the number of bus cycles of internal peripheral bus 1 to 6 differs according to the register to be accessed. when peripheral functions connected to internal peripheral bus 2 to 6 ar e accessed, the number of divided clock synchronization cycles is added. in the peripheral function unit, when the fr equency ratio of iclk is equal to or gr eater than that of pclk (or fclk), the sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will be one cycle of pclk (or fclk) at a maximum. therefore, one pclk (or fclk) has been added to the number of access cycles shown in table 4.1 . note 1. this applies to the number of cycles when the acce ss from the cpu does not conflict with the bus access from the different bus master (dtc). (4) restrictions in relation to rmpa and string-manipulation instructions the allocation of data to be handled by rmpa or string-man ipulation instructions to i/o registers is prohibited, and operation is not guaranteed if this restriction is not observed. (5) notes on sleep mode and mode transitions during sleep mode or mode transitions, do not write to the sy stem control related registers (indicated by 'system' in the module symbol column in table 4.1, list of i/o registers (address order) ).
r01ds0248ej0110 rev.1.10 page 25 of 98 jan 13, 2016 rx23t group 4. i/o registers 4.1 i/o register addresses (address order) table 4.1 list of i/o register s (address order) (1 / 16) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk 0008 0000h system mode monitor register mdmonr 16 16 3 iclk 0008 0008h system system control register 1 syscr1 16 16 3 iclk 0008 000ch system standby control register sbycr 16 16 3 iclk 0008 0010h system module stop control register a mstpcra 32 32 3 iclk 0008 0014h system module stop control register b mstpcrb 32 32 3 iclk 0008 0018h system module stop control register c mstpcrc 32 32 3 iclk 0008 0020h system system clock control register sckcr 32 32 3 iclk 0008 0026h system system clock control register 3 sckcr3 16 16 3 iclk 0008 0028h system pll control register pllcr 16 16 3 iclk 0008 002ah system pll control register 2 pllcr2 8 8 3 iclk 0008 0031h system memory wait cycle setting register memwait 8 8 3 iclk 0008 0032h system main clock oscillator control register mosccr 8 8 3 iclk 0008 0034h system low-speed on-chip oscillator control register lococr 8 8 3 iclk 0008 0035h system iwdt-dedicated on-chip oscillator control register ilococr 8 8 3 iclk 0008 0036h system high-speed on-chip osc illator control register hococr 8 8 3iclk 0008 003ch system oscillation stabilization flag register oscovfsr 8 8 3 iclk 0008 0040h system oscillation stop detection control register ostdcr 8 8 3 iclk 0008 0041h system oscillation stop detection status register ostdsr 8 8 3 iclk 0008 00a0h system operating power control register opccr 8 8 3 iclk 0008 00a2h system main clock oscillator wa it control register moscwtcr 8 8 3 iclk 0008 00a5h system high-speed on-chip oscillato r wait control register hocowtcr 8 8 3iclk 0008 00c0h system reset status register 2 rstsr2 8 8 3 iclk 0008 00c2h system software reset register swrr 16 16 3 iclk 0008 00e0h system voltage monitoring 1 circuit control register 1 lvd1cr1 8 8 3 iclk 0008 00e1h system voltage monitoring 1 circuit status register lvd1sr 8 8 3 iclk 0008 00e2h system voltage monitoring 2 circuit control register 1 lvd2cr1 8 8 3 iclk 0008 00e3h system voltage monitoring 2 circuit status register lvd2sr 8 8 3 iclk 0008 03feh system protect register prcr 16 16 3 iclk 0008 1300h bsc bus error status clear register berclr 8 8 2 iclk 0008 1304h bsc bus error monitoring enable register beren 8 8 2 iclk 0008 1308h bsc bus error status register 1 bersr1 8 8 2 iclk 0008 130ah bsc bus error status register 2 bersr2 16 16 2 iclk 0008 1310h bsc bus priority control register buspri 16 16 2 iclk 0008 2400h dtc dtc control register dtccr 8 8 2 iclk 0008 2404h dtc dtc vector base register dtcvbr 32 32 2 iclk 0008 2408h dtc dtc address mode register dtcadmod 8 8 2 iclk 0008 240ch dtc dtc module start register dtcst 8 8 2 iclk 0008 240eh dtc dtc status register dtcsts 16 16 2 iclk 0008 6400h mpu region-0 start page number register rspage0 32 32 1 iclk 0008 6404h mpu region-0 end page number register repage0 32 32 1 iclk 0008 6408h mpu region-1 start page number register rspage1 32 32 1 iclk 0008 640ch mpu region-1 end page number register repage1 32 32 1 iclk 0008 6410h mpu region-2 start page number register rspage2 32 32 1 iclk 0008 6414h mpu region-2 end page number register repage2 32 32 1 iclk 0008 6418h mpu region-3 start page number register rspage3 32 32 1 iclk 0008 641ch mpu region-3 end page number register repage3 32 32 1 iclk 0008 6420h mpu region-4 start page number register rspage4 32 32 1 iclk 0008 6424h mpu region-4 end page number register repage4 32 32 1 iclk 0008 6428h mpu region-5 start page number register rspage5 32 32 1 iclk
r01ds0248ej0110 rev.1.10 page 26 of 98 jan 13, 2016 rx23t group 4. i/o registers 0008 642ch mpu region-5 end page number register repage5 32 32 1 iclk 0008 6430h mpu region-6 start page number register rspage6 32 32 1 iclk 0008 6434h mpu region-6 end page number register repage6 32 32 1 iclk 0008 6438h mpu region-7 start page number register rspage7 32 32 1 iclk 0008 643ch mpu region-7 end page number register repage7 32 32 1 iclk 0008 6500h mpu memory-protection enable register mpen 32 32 1 iclk 0008 6504h mpu background access control register mpbac 32 32 1 iclk 0008 6508h mpu memory-protection error status-clearing register mpeclr 32 32 1 iclk 0008 650ch mpu memory-protection error status register mpests 32 32 1 iclk 0008 6514h mpu data memory-protection error address register mpdea 32 32 1 iclk 0008 6520h mpu region search address register mpsa 32 32 1 iclk 0008 6524h mpu region search operation register mpops 16 16 1 iclk 0008 6526h mpu region invalidation operation register mpopi 16 16 1 iclk 0008 6528h mpu instruction-hit region register mhiti 32 32 1 iclk 0008 652ch mpu data-hit region register mhitd 32 32 1 iclk 0008 7010h icu interrupt request register 016 ir016 8 8 2 iclk 0008 7017h icu interrupt request register 023 ir023 8 8 2 iclk 0008 701bh icu interrupt request register 027 ir027 8 8 2 iclk 0008 701ch icu interrupt request register 028 ir028 8 8 2 iclk 0008 701dh icu interrupt request register 029 ir029 8 8 2 iclk 0008 701eh icu interrupt request register 030 ir030 8 8 2 iclk 0008 701fh icu interrupt request register 031 ir031 8 8 2 iclk 0008 7020h icu interrupt request register 032 ir032 8 8 2 iclk 0008 7021h icu interrupt request register 033 ir033 8 8 2 iclk 0008 7022h icu interrupt request register 034 ir034 8 8 2 iclk 0008 702ch icu interrupt request register 044 ir044 8 8 2 iclk 0008 702dh icu interrupt request register 045 ir045 8 8 2 iclk 0008 702eh icu interrupt request register 046 ir046 8 8 2 iclk 0008 702fh icu interrupt request register 047 ir047 8 8 2 iclk 0008 7039h icu interrupt request register 057 ir057 8 8 2 iclk 0008 7040h icu interrupt request register 064 ir064 8 8 2 iclk 0008 7041h icu interrupt request register 065 ir065 8 8 2 iclk 0008 7042h icu interrupt request register 066 ir066 8 8 2 iclk 0008 7043h icu interrupt request register 067 ir067 8 8 2 iclk 0008 7044h icu interrupt request register 068 ir068 8 8 2 iclk 0008 7045h icu interrupt request register 069 ir069 8 8 2 iclk 0008 7058h icu interrupt request register 088 ir088 8 8 2 iclk 0008 7059h icu interrupt request register 089 ir089 8 8 2 iclk 0008 7066h icu interrupt request register 102 ir102 8 8 2 iclk 0008 7067h icu interrupt request register 103 ir103 8 8 2 iclk 0008 706ch icu interrupt request register 108 ir108 8 8 2 iclk 0008 706dh icu interrupt request register 109 ir109 8 8 2 iclk 0008 706eh icu interrupt request register 110 ir110 8 8 2 iclk 0008 7072h icu interrupt request register 114 ir114 8 8 2 iclk 0008 7073h icu interrupt request register 115 ir115 8 8 2 iclk 0008 7074h icu interrupt request register 116 ir116 8 8 2 iclk 0008 7075h icu interrupt request register 117 ir117 8 8 2 iclk 0008 7076h icu interrupt request register 118 ir118 8 8 2 iclk 0008 7077h icu interrupt request register 119 ir119 8 8 2 iclk 0008 7078h icu interrupt request register 120 ir120 8 8 2 iclk 0008 7079h icu interrupt request register 121 ir121 8 8 2 iclk 0008 707ah icu interrupt request register 122 ir122 8 8 2 iclk table 4.1 list of i/o register s (address order) (2 / 16) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk
r01ds0248ej0110 rev.1.10 page 27 of 98 jan 13, 2016 rx23t group 4. i/o registers 0008 707bh icu interrupt request register 123 ir123 8 8 2 iclk 0008 707ch icu interrupt request register 124 ir124 8 8 2 iclk 0008 707dh icu interrupt request register 125 ir125 8 8 2 iclk 0008 707eh icu interrupt request register 126 ir126 8 8 2 iclk 0008 707fh icu interrupt request register 127 ir127 8 8 2 iclk 0008 7080h icu interrupt request register 128 ir128 8 8 2 iclk 0008 7081h icu interrupt request register 129 ir129 8 8 2 iclk 0008 7082h icu interrupt request register 130 ir130 8 8 2 iclk 0008 7083h icu interrupt request register 131 ir131 8 8 2 iclk 0008 7084h icu interrupt request register 132 ir132 8 8 2 iclk 0008 7085h icu interrupt request register 133 ir133 8 8 2 iclk 0008 7086h icu interrupt request register 134 ir134 8 8 2 iclk 0008 7087h icu interrupt request register 135 ir135 8 8 2 iclk 0008 7088h icu interrupt request register 136 ir136 8 8 2 iclk 0008 7089h icu interrupt request register 137 ir137 8 8 2 iclk 0008 708ah icu interrupt request register 138 ir138 8 8 2 iclk 0008 708bh icu interrupt request register 139 ir139 8 8 2 iclk 0008 708ch icu interrupt request register 140 ir140 8 8 2 iclk 0008 708dh icu interrupt request register 141 ir141 8 8 2 iclk 0008 70a8h icu interrupt request register 168 ir168 8 8 2 iclk 0008 70aah icu interrupt request register 170 ir170 8 8 2 iclk 0008 70abh icu interrupt request register 171 ir171 8 8 2 iclk 0008 70aeh icu interrupt request register 174 ir174 8 8 2 iclk 0008 70afh icu interrupt request register 175 ir175 8 8 2 iclk 0008 70b0h icu interrupt request register 176 ir176 8 8 2 iclk 0008 70b1h icu interrupt request register 177 ir177 8 8 2 iclk 0008 70b2h icu interrupt request register 178 ir178 8 8 2 iclk 0008 70b3h icu interrupt request register 179 ir179 8 8 2 iclk 0008 70b4h icu interrupt request register 180 ir180 8 8 2 iclk 0008 70b5h icu interrupt request register 181 ir181 8 8 2 iclk 0008 70b6h icu interrupt request register 182 ir182 8 8 2 iclk 0008 70b7h icu interrupt request register 183 ir183 8 8 2 iclk 0008 70b8h icu interrupt request register 184 ir184 8 8 2 iclk 0008 70b9h icu interrupt request register 185 ir185 8 8 2 iclk 0008 70dah icu interrupt request register 218 ir218 8 8 2 iclk 0008 70dbh icu interrupt request register 219 ir219 8 8 2 iclk 0008 70dch icu interrupt request register 220 ir220 8 8 2 iclk 0008 70ddh icu interrupt request register 221 ir221 8 8 2 iclk 0008 70deh icu interrupt request register 222 ir222 8 8 2 iclk 0008 70dfh icu interrupt request register 223 ir223 8 8 2 iclk 0008 70e0h icu interrupt request register 224 ir224 8 8 2 iclk 0008 70e1h icu interrupt request register 225 ir225 8 8 2 iclk 0008 70f6h icu interrupt request register 246 ir246 8 8 2 iclk 0008 70f7h icu interrupt request register 247 ir247 8 8 2 iclk 0008 70f8h icu interrupt request register 248 ir248 8 8 2 iclk 0008 70f9h icu interrupt request register 249 ir249 8 8 2 iclk 0008 711bh icu dtc activation enable register 027 dtcer027 8 8 2 iclk 0008 711ch icu dtc activation enable register 028 dtcer028 8 8 2 iclk 0008 711dh icu dtc activation enable register 029 dtcer029 8 8 2 iclk 0008 711eh icu dtc activation enable register 030 dtcer030 8 8 2 iclk 0008 711fh icu dtc activation enable register 031 dtcer031 8 8 2 iclk 0008 712dh icu dtc activation enable register 045 dtcer045 8 8 2 iclk table 4.1 list of i/o register s (address order) (3 / 16) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk
r01ds0248ej0110 rev.1.10 page 28 of 98 jan 13, 2016 rx23t group 4. i/o registers 0008 712eh icu dtc activation enable register 046 dtcer046 8 8 2 iclk 0008 7140h icu dtc activation enable register 064 dtcer064 8 8 2 iclk 0008 7141h icu dtc activation enable register 065 dtcer065 8 8 2 iclk 0008 7142h icu dtc activation enable register 066 dtcer066 8 8 2 iclk 0008 7143h icu dtc activation enable register 067 dtcer067 8 8 2 iclk 0008 7144h icu dtc activation enable register 068 dtcer068 8 8 2 iclk 0008 7145h icu dtc activation enable register 069 dtcer069 8 8 2 iclk 0008 7166h icu dtc activation enable register 102 dtcer102 8 8 2 iclk 0008 7167h icu dtc activation enable register 103 dtcer103 8 8 2 iclk 0008 716ch icu dtc activation enable register 108 dtcer108 8 8 2 iclk 0008 716dh icu dtc activation enable register 109 dtcer109 8 8 2 iclk 0008 716eh icu dtc activation enable register 110 dtcer110 8 8 2 iclk 0008 7172h icu dtc activation enable register 114 dtcer114 8 8 2 iclk 0008 7173h icu dtc activation enable register 115 dtcer115 8 8 2 iclk 0008 7174h icu dtc activation enable register 116 dtcer116 8 8 2 iclk 0008 7175h icu dtc activation enable register 117 dtcer117 8 8 2 iclk 0008 7179h icu dtc activation enable register 121 dtcer121 8 8 2 iclk 0008 717ah icu dtc activation enable register 122 dtcer122 8 8 2 iclk 0008 717dh icu dtc activation enable register 125 dtcer125 8 8 2 iclk 0008 717eh icu dtc activation enable register 126 dtcer126 8 8 2 iclk 0008 7181h icu dtc activation enable register 129 dtcer129 8 8 2 iclk 0008 7182h icu dtc activation enable register 130 dtcer130 8 8 2 iclk 0008 7183h icu dtc activation enable register 131 dtcer131 8 8 2 iclk 0008 7184h icu dtc activation enable register 132 dtcer132 8 8 2 iclk 0008 7186h icu dtc activation enable register 134 dtcer134 8 8 2 iclk 0008 7187h icu dtc activation enable register 135 dtcer135 8 8 2 iclk 0008 7188h icu dtc activation enable register 136 dtcer136 8 8 2 iclk 0008 7189h icu dtc activation enable register 137 dtcer137 8 8 2 iclk 0008 718ah icu dtc activation enable register 138 dtcer138 8 8 2 iclk 0008 718bh icu dtc activation enable register 139 dtcer139 8 8 2 iclk 0008 718ch icu dtc activation enable register 140 dtcer140 8 8 2 iclk 0008 718dh icu dtc activation enable register 141 dtcer141 8 8 2 iclk 0008 71aeh icu dtc activation enable register 174 dtcer174 8 8 2 iclk 0008 71afh icu dtc activation enable register 175 dtcer175 8 8 2 iclk 0008 71b1h icu dtc activation enable register 177 dtcer177 8 8 2 iclk 0008 71b2h icu dtc activation enable register 178 dtcer178 8 8 2 iclk 0008 71b4h icu dtc activation enable register 180 dtcer180 8 8 2 iclk 0008 71b5h icu dtc activation enable register 181 dtcer181 8 8 2 iclk 0008 71b7h icu dtc activation enable register 183 dtcer183 8 8 2 iclk 0008 71b8h icu dtc activation enable register 184 dtcer184 8 8 2 iclk 0008 71dbh icu dtc activation enable register 219 dtcer219 8 8 2 iclk 0008 71dch icu dtc activation enable register 220 dtcer220 8 8 2 iclk 0008 71dfh icu dtc activation enable register 223 dtcer223 8 8 2 iclk 0008 71e0h icu dtc activation enable register 224 dtcer224 8 8 2 iclk 0008 71f7h icu dtc activation enable register 247 dtcer247 8 8 2 iclk 0008 71f8h icu dtc activation enable register 248 dtcer248 8 8 2 iclk 0008 7202h icu interrupt request enable register 02 ier02 8 8 2 iclk 0008 7203h icu interrupt request enable register 03 ier03 8 8 2 iclk 0008 7204h icu interrupt request enable register 04 ier04 8 8 2 iclk 0008 7205h icu interrupt request enable register 05 ier05 8 8 2 iclk 0008 7207h icu interrupt request enable register 07 ier07 8 8 2 iclk 0008 7208h icu interrupt request enable register 08 ier08 8 8 2 iclk table 4.1 list of i/o register s (address order) (4 / 16) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk
r01ds0248ej0110 rev.1.10 page 29 of 98 jan 13, 2016 rx23t group 4. i/o registers 0008 720bh icu interrupt request enable register 0b ier0b 8 8 2 iclk 0008 720ch icu interrupt request enable register 0c ier0c 8 8 2 iclk 0008 720dh icu interrupt request enable register 0d ier0d 8 8 2 iclk 0008 720eh icu interrupt request enable register 0e ier0e 8 8 2 iclk 0008 720fh icu interrupt request enable register 0f ier0f 8 8 2 iclk 0008 7210h icu interrupt request enable register 10 ier10 8 8 2 iclk 0008 7211h icu interrupt request enable register 11 ier11 8 8 2 iclk 0008 7215h icu interrupt request enable register 15 ier15 8 8 2 iclk 0008 7216h icu interrupt request enable register 16 ier16 8 8 2 iclk 0008 7217h icu interrupt request enable register 17 ier17 8 8 2 iclk 0008 721bh icu interrupt request enable register 1b ier1b 8 8 2 iclk 0008 721ch icu interrupt request enable register 1c ier1c 8 8 2 iclk 0008 721eh icu interrupt request enable register 1e ier1e 8 8 2 iclk 0008 721fh icu interrupt request enable register 1f ier1f 8 8 2 iclk 0008 72e0h icu software interrupt activation register swintr 8 8 2 iclk 0008 72f0h icu fast interrupt set register fir 16 16 2 iclk 0008 7300h icu interrupt source priority register 000 ipr000 8 8 2 iclk 0008 7302h icu interrupt source priority register 002 ipr002 8 8 2 iclk 0008 7303h icu interrupt source priority register 003 ipr003 8 8 2 iclk 0008 7304h icu interrupt source priority register 004 ipr004 8 8 2 iclk 0008 7305h icu interrupt source priority register 005 ipr005 8 8 2 iclk 0008 7306h icu interrupt source priority register 006 ipr006 8 8 2 iclk 0008 7307h icu interrupt source priority register 007 ipr007 8 8 2 iclk 0008 7320h icu interrupt source priority register 032 ipr032 8 8 2 iclk 0008 7321h icu interrupt source priority register 033 ipr033 8 8 2 iclk 0008 7322h icu interrupt source priority register 034 ipr034 8 8 2 iclk 0008 732ch icu interrupt source priority register 044 ipr044 8 8 2 iclk 0008 7339h icu interrupt source priority register 057 ipr057 8 8 2 iclk 0008 7340h icu interrupt source priority register 064 ipr064 8 8 2 iclk 0008 7341h icu interrupt source priority register 065 ipr065 8 8 2 iclk 0008 7342h icu interrupt source priority register 066 ipr066 8 8 2 iclk 0008 7343h icu interrupt source priority register 067 ipr067 8 8 2 iclk 0008 7344h icu interrupt source priority register 068 ipr068 8 8 2 iclk 0008 7345h icu interrupt source priority register 069 ipr069 8 8 2 iclk 0008 7358h icu interrupt source priority register 088 ipr088 8 8 2 iclk 0008 7359h icu interrupt source priority register 089 ipr089 8 8 2 iclk 0008 7366h icu interrupt source priority register 102 ipr102 8 8 2 iclk 0008 7367h icu interrupt source priority register 103 ipr103 8 8 2 iclk 0008 736ch icu interrupt source priority register 108 ipr108 8 8 2 iclk 0008 736dh icu interrupt source priority register 109 ipr109 8 8 2 iclk 0008 736eh icu interrupt source priority register 110 ipr110 8 8 2 iclk 0008 7372h icu interrupt source priority register 114 ipr114 8 8 2 iclk 0008 7376h icu interrupt source priority register 118 ipr118 8 8 2 iclk 0008 7379h icu interrupt source priority register 121 ipr121 8 8 2 iclk 0008 737bh icu interrupt source priority register 123 ipr123 8 8 2 iclk 0008 737dh icu interrupt source priority register 125 ipr125 8 8 2 iclk 0008 737fh icu interrupt source priority register 127 ipr127 8 8 2 iclk 0008 7381h icu interrupt source priority register 129 ipr129 8 8 2 iclk 0008 7385h icu interrupt source priority register 133 ipr133 8 8 2 iclk 0008 7386h icu interrupt source priority register 134 ipr134 8 8 2 iclk 0008 738ah icu interrupt source priority register 138 ipr138 8 8 2 iclk 0008 738bh icu interrupt source priority register 139 ipr139 8 8 2 iclk table 4.1 list of i/o register s (address order) (5 / 16) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk
r01ds0248ej0110 rev.1.10 page 30 of 98 jan 13, 2016 rx23t group 4. i/o registers 0008 73a8h icu interrupt source priority register 168 ipr168 8 8 2 iclk 0008 73aeh icu interrupt source priority register 174 ipr174 8 8 2 iclk 0008 73b1h icu interrupt source priority register 177 ipr177 8 8 2 iclk 0008 73b4h icu interrupt source priority register 180 ipr180 8 8 2 iclk 0008 73b7h icu interrupt source priority register 183 ipr183 8 8 2 iclk 0008 73dah icu interrupt source priority register 218 ipr218 8 8 2 iclk 0008 73deh icu interrupt source priority register 222 ipr222 8 8 2 iclk 0008 73f6h icu interrupt source priority register 246 ipr246 8 8 2 iclk 0008 73f7h icu interrupt source priority register 247 ipr247 8 8 2 iclk 0008 73f8h icu interrupt source priority register 248 ipr248 8 8 2 iclk 0008 73f9h icu interrupt source priority register 249 ipr249 8 8 2 iclk 0008 7500h icu irq control register 0 irqcr0 8 8 2 iclk 0008 7501h icu irq control register 1 irqcr1 8 8 2 iclk 0008 7502h icu irq control register 2 irqcr2 8 8 2 iclk 0008 7503h icu irq control register 3 irqcr3 8 8 2 iclk 0008 7504h icu irq control register 4 irqcr4 8 8 2 iclk 0008 7505h icu irq control register 5 irqcr5 8 8 2 iclk 0008 7510h icu irq pin digital filter enable register 0 irqflte0 8 8 2 iclk 0008 7514h icu irq pin digital filter setting register 0 irqfltc0 16 16 2 iclk 0008 7580h icu non-maskable interrupt status register nmisr 8 8 2 iclk 0008 7581h icu non-maskable interrupt enable register nmier 8 8 2 iclk 0008 7582h icu non-maskable interrupt status clear register nmiclr 8 8 2 iclk 0008 7583h icu nmi pin interrupt control register nmicr 8 8 2 iclk 0008 7590h icu nmi pin digital filter enable register nmiflte 8 8 2 iclk 0008 7594h icu nmi pin digital filter setting register nmifltc 8 8 2 iclk 0008 8000h cmt compare match timer start register 0 cmstr0 16 16 2 or 3 pclkb 0008 8002h cmt0 compare match timer control register cmcr 16 16 2 or 3 pclkb 0008 8004h cmt0 compare match counter cmcnt 16 16 2 or 3 pclkb 0008 8006h cmt0 compare match constant register cmcor 16 16 2 or 3 pclkb 0008 8008h cmt1 compare match timer control register cmcr 16 16 2 or 3 pclkb 0008 800ah cmt1 compare match counter cmcnt 16 16 2 or 3 pclkb 0008 800ch cmt1 compare match constant register cmcor 16 16 2 or 3 pclkb 0008 8010h cmt compare match timer start register 1 cmstr1 16 16 2 or 3 pclkb 0008 8012h cmt2 compare match timer control register cmcr 16 16 2 or 3 pclkb 0008 8014h cmt2 compare match counter cmcnt 16 16 2 or 3 pclkb 0008 8016h cmt2 compare match constant register cmcor 16 16 2 or 3 pclkb 0008 8018h cmt3 compare match timer control register cmcr 16 16 2 or 3 pclkb 0008 801ah cmt3 compare match counter cmcnt 16 16 2 or 3 pclkb 0008 801ch cmt3 compare match constant register cmcor 16 16 2 or 3 pclkb 0008 8030h iwdt iwdt refresh register iwdtrr 8 8 2 or 3 pclkb 0008 8032h iwdt iwdt control register iwdtcr 16 16 2 or 3 pclkb 0008 8034h iwdt iwdt status register iwdtsr 16 16 2 or 3 pclkb 0008 8036h iwdt iwdt reset control register iwdtrcr 8 8 2 or 3 pclkb 0008 8038h iwdt iwdt count stop control register iwdtcstpr 8 8 2 or 3 pclkb 0008 80c0h da d/a data register 0 dadr0 16 16 2 or 3 pclkb 0008 80c4h da d/a control register dacr 8 8 2 or 3 pclkb 0008 80c5h da dadr0 format select register dadpr 8 8 2 or 3 pclkb 0008 8200h tmr0 timer control register tcr 8 8 2 or 3 pclkb 0008 8201h tmr1 timer control register tcr 8 8 2 or 3 pclkb 0008 8202h tmr0 timer control/status register tcsr 8 8 2 or 3 pclkb 0008 8203h tmr1 timer control/status register tcsr 8 8 2 or 3 pclkb 0008 8204h tmr0 time constant register a tcora 8 8 2 or 3 pclkb table 4.1 list of i/o register s (address order) (6 / 16) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk
r01ds0248ej0110 rev.1.10 page 31 of 98 jan 13, 2016 rx23t group 4. i/o registers 0008 8205h tmr1 time constant register a tcora 8 8* 1 2 or 3 pclkb 0008 8206h tmr0 time constant register b tcorb 8 8 2 or 3 pclkb 0008 8207h tmr1 time constant register b tcorb 8 8* 1 2 or 3 pclkb 0008 8208h tmr0 timer counter tcnt 8 8 2 or 3 pclkb 0008 8209h tmr1 timer counter tcnt 8 8* 1 2 or 3 pclkb 0008 820ah tmr0 timer counter control register tccr 8 8 2 or 3 pclkb 0008 820bh tmr1 timer counter control register tccr 8 8* 1 2 or 3 pclkb 0008 8210h tmr2 timer control register tcr 8 8 2 or 3 pclkb 0008 8211h tmr3 timer control register tcr 8 8 2 or 3 pclkb 0008 8212h tmr2 timer control/status register tcsr 8 8 2 or 3 pclkb 0008 8213h tmr3 timer control/status register tcsr 8 8 2 or 3 pclkb 0008 8214h tmr2 time constant register a tcora 8 8 2 or 3 pclkb 0008 8215h tmr3 time constant register a tcora 8 8* 1 2 or 3 pclkb 0008 8216h tmr2 time constant register b tcorb 8 8 2 or 3 pclkb 0008 8217h tmr3 time constant register b tcorb 8 8* 1 2 or 3 pclkb 0008 8218h tmr2 timer counter tcnt 8 8 2 or 3 pclkb 0008 8219h tmr3 timer counter tcnt 8 8* 1 2 or 3 pclkb 0008 821ah tmr2 timer counter control register tccr 8 8 2 or 3 pclkb 0008 821bh tmr3 timer counter control register tccr 8 8* 1 2 or 3 pclkb 0008 8280h crc crc control register crccr 8 8 2 or 3 pclkb 0008 8281h crc crc data input register crcdir 8 8 2 or 3 pclkb 0008 8282h crc crc data output register crcdor 16 16 2 or 3 pclkb 0008 8300h riic0 i 2 c bus control register 1 iccr1 8 8 2 or 3 pclkb 0008 8301h riic0 i 2 c bus control register 2 iccr2 8 8 2 or 3 pclkb 0008 8302h riic0 i 2 c bus mode register 1 icmr1 8 8 2 or 3 pclkb 0008 8303h riic0 i 2 c bus mode register 2 icmr2 8 8 2 or 3 pclkb 0008 8304h riic0 i 2 c bus mode register 3 icmr3 8 8 2 or 3 pclkb 0008 8305h riic0 i 2 c bus function enable register icfer 8 8 2 or 3 pclkb 0008 8306h riic0 i 2 c bus status enable register icser 8 8 2 or 3 pclkb 0008 8307h riic0 i 2 c bus interrupt enable register icier 8 8 2 or 3 pclkb 0008 8308h riic0 i 2 c bus status register 1 icsr1 8 8 2 or 3 pclkb 0008 8309h riic0 i 2 c bus status register 2 icsr2 8 8 2 or 3 pclkb 0008 830ah riic0 slave address register l0 sarl0 8 8 2 or 3 pclkb 0008 830bh riic0 slave address register u0 saru0 8 8 2 or 3 pclkb 0008 830ch riic0 slave address register l1 sarl1 8 8 2 or 3 pclkb 0008 830dh riic0 slave address register u1 saru1 8 8 2 or 3 pclkb 0008 830eh riic0 slave address register l2 sarl2 8 8 2 or 3 pclkb 0008 830fh riic0 slave address register u2 saru2 8 8 2 or 3 pclkb 0008 8310h riic0 i 2 c bus bit rate low-level register icbrl 8 8 2 or 3 pclkb 0008 8311h riic0 i 2 c bus bit rate high-level register icbrh 8 8 2 or 3 pclkb 0008 8312h riic0 i 2 c bus transmit data register icdrt 8 8 2 or 3 pclkb 0008 8313h riic0 i 2 c bus receive data register icdrr 8 8 2 or 3 pclkb 0008 8380h rspi0 rspi control register spcr 8 8 2 or 3 pclkb 0008 8381h rspi0 rspi slave select polarity register sslp 8 8 2 or 3 pclkb 0008 8382h rspi0 rspi pin control register sppcr 8 8 2 or 3 pclkb 0008 8383h rspi0 rspi status register spsr 8 8 2 or 3 pclkb 0008 8384h rspi0 rspi data register spdr 32 16, 32 2 or 3 pclkb 0008 8388h rspi0 rspi sequence control register spscr 8 8 2 or 3 pclkb 0008 8389h rspi0 rspi sequence status register spssr 8 8 2 or 3 pclkb 0008 838ah rspi0 rspi bit rate register spbr 8 8 2 or 3 pclkb 0008 838bh rspi0 rspi data control register spdcr 8 8 2 or 3 pclkb 0008 838ch rspi0 rspi clock delay register spckd 8 8 2 or 3 pclkb table 4.1 list of i/o register s (address order) (7 / 16) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk
r01ds0248ej0110 rev.1.10 page 32 of 98 jan 13, 2016 rx23t group 4. i/o registers 0008 838dh rspi0 rspi slave select negation delay register sslnd 8 8 2 or 3 pclkb 0008 838eh rspi0 rspi next-access delay register spnd 8 8 2 or 3 pclkb 0008 838fh rspi0 rspi control register 2 spcr2 8 8 2 or 3 pclkb 0008 8390h rspi0 rspi command register 0 spcmd0 16 16 2 or 3 pclkb 0008 8392h rspi0 rspi command register 1 spcmd1 16 16 2 or 3 pclkb 0008 8394h rspi0 rspi command register 2 spcmd2 16 16 2 or 3 pclkb 0008 8396h rspi0 rspi command register 3 spcmd3 16 16 2 or 3 pclkb 0008 8398h rspi0 rspi command register 4 spcmd4 16 16 2 or 3 pclkb 0008 839ah rspi0 rspi command register 5 spcmd5 16 16 2 or 3 pclkb 0008 839ch rspi0 rspi command register 6 spcmd6 16 16 2 or 3 pclkb 0008 839eh rspi0 rspi command register 7 spcmd7 16 16 2 or 3 pclkb 0008 9000h s12ad a/d control register adcsr 16 16 2 or 3 pclkb 0008 9004h s12ad a/d channel select register a0 adansa0 16 16 2 or 3 pclkb 0008 9006h s12ad a/d channel select register a1 adansa1 16 16 2 or 3 pclkb 0008 9008h s12ad a/d-converted value addition/average function select register 0 adads0 16 16 2 or 3 pclkb 0008 900ah s12ad a/d-converted value addition/average function select register 1 adads1 16 16 2 or 3 pclkb 0008 900ch s12ad a/d-converted value addition/average count select register adadc 8 8 2 or 3 pclkb 0008 900eh s12ad a/d control extended register adcer 16 16 2 or 3 pclkb 0008 9010h s12ad a/d conversion start trigger select register adstrgr 16 16 2 or 3 pclkb 0008 9012h s12ad a/d conversion extended input control register adexicr 16 16 2 or 3 pclkb 0008 9014h s12ad a/d channel select register b0 adansb0 16 16 2 or 3 pclkb 0008 9016h s12ad a/d channel select register b1 adansb1 16 16 2 or 3 pclkb 0008 9018h s12ad a/d data duplication register addbldr 16 16 2 or 3 pclkb 0008 901ch s12ad a/d internal reference voltage data register adocdr 16 16 2 or 3 pclkb 0008 901eh s12ad a/d self-diagnosis data register adrd 16 16 2 or 3 pclkb 0008 9020h s12ad a/d data register 0 addr0 16 16 2 or 3 pclkb 0008 9022h s12ad a/d data register 1 addr1 16 16 2 or 3 pclkb 0008 9024h s12ad a/d data register 2 addr2 16 16 2 or 3 pclkb 0008 9026h s12ad a/d data register 3 addr3 16 16 2 or 3 pclkb 0008 9028h s12ad a/d data register 4 addr4 16 16 2 or 3 pclkb 0008 902ah s12ad a/d data register 5 addr5 16 16 2 or 3 pclkb 0008 902ch s12ad a/d data register 6 addr6 16 16 2 or 3 pclkb 0008 902eh s12ad a/d data register 7 addr7 16 16 2 or 3 pclkb 0008 9040h s12ad a/d data register 16 addr16 16 16 2 or 3 pclkb 0008 9042h s12ad a/d data register 17 addr17 16 16 2 or 3 pclkb 0008 9066h s12ad a/d sample-and-hold circuit control register adshcr 16 16 2 or 3 pclkb 0008 907ah s12ad a/d disconnection detection control register addiscr 8 8 2 or 3 pclkb 0008 9080h s12ad a/d group scan priority control register adgspcr 16 16 2 or 3 pclkb 0008 9084h s12ad a/d data duplication register a addbldra 16 16 2 or 3 pclkb 0008 9086h s12ad a/d data duplication register b addbldrb 16 16 2 or 3 pclkb 0008 908ah s12ad a/d high-side/low-side reference voltage control register adhvrefcnt 8 8 2 or 3 pclkb 0008 90ddh s12ad a/d sampling state register l adsstrl 8 8 2 or 3 pclkb 0008 90dfh s12ad a/d sampling state register o adsstro 8 8 2 or 3 pclkb 0008 90e0h s12ad a/d sampling state register 0 adsstr0 8 8 2 or 3 pclkb 0008 90e1h s12ad a/d sampling state register 1 adsstr1 8 8 2 or 3 pclkb 0008 90e2h s12ad a/d sampling state register 2 adsstr2 8 8 2 or 3 pclkb 0008 90e3h s12ad a/d sampling state register 3 adsstr3 8 8 2 or 3 pclkb 0008 90e4h s12ad a/d sampling state register 4 adsstr4 8 8 2 or 3 pclkb 0008 90e5h s12ad a/d sampling state register 5 adsstr5 8 8 2 or 3 pclkb 0008 90e6h s12ad a/d sampling state register 6 adsstr6 8 8 2 or 3 pclkb table 4.1 list of i/o register s (address order) (8 / 16) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk
r01ds0248ej0110 rev.1.10 page 33 of 98 jan 13, 2016 rx23t group 4. i/o registers 0008 90e7h s12ad a/d sampling state register 7 adsstr7 8 8 2 or 3 pclkb 0008 a020h sci1 serial mode register smr 8 8 2 or 3 pclkb 0008 a021h sci1 bit rate register brr 8 8 2 or 3 pclkb 0008 a022h sci1 serial control register scr 8 8 2 or 3 pclkb 0008 a023h sci1 transmit data register tdr 8 8 2 or 3 pclkb 0008 a024h sci1 serial status register ssr 8 8 2 or 3 pclkb 0008 a025h sci1 receive data register rdr 8 8 2 or 3 pclkb 0008 a026h sci1 smart card mode register scmr 8 8 2 or 3 pclkb 0008 a027h sci1 serial extended mode register semr 8 8 2 or 3 pclkb 0008 a028h sci1 noise filter setting register snfr 8 8 2 or 3 pclkb 0008 a029h sci1 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 0008 a02ah sci1 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 0008 a02bh sci1 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 0008 a02ch sci1 i 2 c status register sisr 8 8 2 or 3 pclkb 0008 a02dh sci1 spi mode register spmr 8 8 2 or 3 pclkb 0008 a02eh sci1 transmit data register hl tdrhl 16 16 4 or 5 pclkb 0008 a02eh sci1 transmit data register h tdrh 8 8 2 or 3 pclkb 0008 a02fh sci1 transmit data register l tdrl 8 8 2 or 3 pclkb 0008 a030h sci1 receive data register hl rdrhl 16 16 4 or 5 pclkb 0008 a030h sci1 receive data register h rdrh 8 8 2 or 3 pclkb 0008 a031h sci1 receive data register l rdrl 8 8 2 or 3 pclkb 0008 a032h sci1 modulation duty register mddr 8 8 2 or 3 pclkb 0008 a0a0h sci5 serial mode register smr 8 8 2 or 3 pclkb 0008 a0a1h sci5 bit rate register brr 8 8 2 or 3 pclkb 0008 a0a2h sci5 serial control register scr 8 8 2 or 3 pclkb 0008 a0a3h sci5 transmit data register tdr 8 8 2 or 3 pclkb 0008 a0a4h sci5 serial status register ssr 8 8 2 or 3 pclkb 0008 a0a5h sci5 receive data register rdr 8 8 2 or 3 pclkb 0008 a0a6h sci5 smart card mode register scmr 8 8 2 or 3 pclkb 0008 a0a7h sci5 serial extended mode register semr 8 8 2 or 3 pclkb 0008 a0a8h sci5 noise filter setting register snfr 8 8 2 or 3 pclkb 0008 a0a9h sci5 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 0008 a0aah sci5 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 0008 a0abh sci5 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 0008 a0ach sci5 i 2 c status register sisr 8 8 2 or 3 pclkb 0008 a0adh sci5 spi mode register spmr 8 8 2 or 3 pclkb 0008 a0aeh sci5 transmit data register hl tdrhl 16 16 4 or 5 pclkb 0008 a0aeh sci5 transmit data register h tdrh 8 8 2 or 3 pclkb 0008 a0afh sci5 transmit data register l tdrl 8 8 2 or 3 pclkb 0008 a0b0h sci5 receive data register hl rdrhl 16 16 4 or 5 pclkb 0008 a0b0h sci5 receive data register h rdrh 8 8 2 or 3 pclkb 0008 a0b1h sci5 receive data register l rdrl 8 8 2 or 3 pclkb 0008 a0b2h sci5 modulation duty register mddr 8 8 2 or 3 pclkb 0008 b000h cac cac control register 0 cacr0 8 8 2 or 3 pclkb 0008 b001h cac cac control register 1 cacr1 8 8 2 or 3 pclkb 0008 b002h cac cac control register 2 cacr2 8 8 2 or 3 pclkb 0008 b003h cac cac interrupt request enable register caicr 8 8 2 or 3 pclkb 0008 b004h cac cac status register castr 8 8 2 or 3 pclkb 0008 b006h cac cac upper-limit value setting register caulvr 16 16 2 or 3 pclkb 0008 b008h cac cac lower-limit value setting register callvr 16 16 2 or 3 pclkb 0008 b00ah cac cac counter buffer register cacntbr 16 16 2 or 3 pclkb 0008 b080h doc doc control register docr 8 8 2 or 3 pclkb table 4.1 list of i/o register s (address order) (9 / 16) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk
r01ds0248ej0110 rev.1.10 page 34 of 98 jan 13, 2016 rx23t group 4. i/o registers 0008 b082h doc doc data input register dodir 16 16 2 or 3 pclkb 0008 b084h doc doc data setting register dodsr 16 16 2 or 3 pclkb 0008 c000h port0 port direction register pdr 8 8 2 or 3 pclkb 0008 c001h port1 port direction register pdr 8 8 2 or 3 pclkb 0008 c002h port2 port direction register pdr 8 8 2 or 3 pclkb 0008 c003h port3 port direction register pdr 8 8 2 or 3 pclkb 0008 c004h port4 port direction register pdr 8 8 2 or 3 pclkb 0008 c007h port7 port direction register pdr 8 8 2 or 3 pclkb 0008 c009h port9 port direction register pdr 8 8 2 or 3 pclkb 0008 c00ah porta port direction register pdr 8 8 2 or 3 pclkb 0008 c00bh portb port direction register pdr 8 8 2 or 3 pclkb 0008 c00dh portd port direction register pdr 8 8 2 or 3 pclkb 0008 c020h port0 port output data register podr 8 8 2 or 3 pclkb 0008 c021h port1 port output data register podr 8 8 2 or 3 pclkb 0008 c022h port2 port output data register podr 8 8 2 or 3 pclkb 0008 c023h port3 port output data register podr 8 8 2 or 3 pclkb 0008 c024h port4 port output data register podr 8 8 2 or 3 pclkb 0008 c027h port7 port output data register podr 8 8 2 or 3 pclkb 0008 c029h port9 port output data register podr 8 8 2 or 3 pclkb 0008 c02ah porta port output data register podr 8 8 2 or 3 pclkb 0008 c02bh portb port output data register podr 8 8 2 or 3 pclkb 0008 c02dh portd port output data register podr 8 8 2 or 3 pclkb 0008 c040h port0 port input data register pidr 8 8 2 or 3 pclkb 0008 c041h port1 port input data register pidr 8 8 2 or 3 pclkb 0008 c042h port2 port input data register pidr 8 8 2 or 3 pclkb 0008 c043h port3 port input data register pidr 8 8 2 or 3 pclkb 0008 c044h port4 port input data register pidr 8 8 2 or 3 pclkb 0008 c047h port7 port input data register pidr 8 8 2 or 3 pclkb 0008 c049h port9 port input data register pidr 8 8 2 or 3 pclkb 0008 c04ah porta port input data register pidr 8 8 2 or 3 pclkb 0008 c04bh portb port input data register pidr 8 8 2 or 3 pclkb 0008 c04dh portd port input data register pidr 8 8 2 or 3 pclkb 0008 c04eh porte port input data register pidr 8 8 2 or 3 pclkb 0008 c060h port0 port mode register pmr 8 8 2 or 3 pclkb 0008 c061h port1 port mode register pmr 8 8 2 or 3 pclkb 0008 c062h port2 port mode register pmr 8 8 2 or 3 pclkb 0008 c063h port3 port mode register pmr 8 8 2 or 3 pclkb 0008 c067h port7 port mode register pmr 8 8 2 or 3 pclkb 0008 c069h port9 port mode register pmr 8 8 2 or 3 pclkb 0008 c06ah porta port mode register pmr 8 8 2 or 3 pclkb 0008 c06bh portb port mode register pmr 8 8 2 or 3 pclkb 0008 c06dh portd port mode register pmr 8 8 2 or 3 pclkb 0008 c06eh porte port mode register pmr 8 8 2 or 3 pclkb 0008 c080h port0 open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c082h port1 open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c084h port2 open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c085h port2 open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 0008 c086h port3 open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c087h port3 open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 0008 c08eh port7 open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c08fh port7 open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 0008 c092h port9 open drain control register 0 odr0 8 8, 16 2 or 3 pclkb table 4.1 list of i/o register s (address order) (10 / 16) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk
r01ds0248ej0110 rev.1.10 page 35 of 98 jan 13, 2016 rx23t group 4. i/o registers 0008 c093h port9 open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 0008 c094h porta open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c095h porta open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 0008 c096h portb open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c097h portb open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 0008 c09ah portd open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c09bh portd open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 0008 c0c0h port0 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c1h port1 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c2h port2 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c3h port3 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c4h port4 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c7h port7 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c9h port9 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0cah porta pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0cbh portb pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0cdh portd pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0e0h port0 drive capacity control register dscr 8 8 2 or 3 pclkb 0008 c0e1h port1 drive capacity control register dscr 8 8 2 or 3 pclkb 0008 c0e2h port2 drive capacity control register dscr 8 8 2 or 3 pclkb 0008 c0e3h port3 drive capacity control register dscr 8 8 2 or 3 pclkb 0008 c0e7h port7 drive capacity control register dscr 8 8 2 or 3 pclkb 0008 c0e9h port9 drive capacity control register dscr 8 8 2 or 3 pclkb 0008 c0eah porta drive capacity control register dscr 8 8 2 or 3 pclkb 0008 c0ebh portb drive capacity control register dscr 8 8 2 or 3 pclkb 0008 c0edh portd drive capacity control register dscr 8 8 2 or 3 pclkb 0008 c11fh mpc write-protect register pwpr 8 8 2 or 3 pclkb 0008 c140h mpc p00 pin function control register p00pfs 8 8 2 or 3 pclkb 0008 c141h mpc p01 pin function control register p01pfs 8 8 2 or 3 pclkb 0008 c142h mpc p02 pin function control register p02pfs 8 8 2 or 3 pclkb 0008 c148h mpc p10 pin function control register p10pfs 8 8 2 or 3 pclkb 0008 c149h mpc p11 pin function control register p11pfs 8 8 2 or 3 pclkb 0008 c152h mpc p22 pin function control register p22pfs 8 8 2 or 3 pclkb 0008 c153h mpc p23 pin function control register p23pfs 8 8 2 or 3 pclkb 0008 c154h mpc p24 pin function control register p24pfs 8 8 2 or 3 pclkb 0008 c158h mpc p30 pin function control register p30pfs 8 8 2 or 3 pclkb 0008 c159h mpc p31 pin function control register p31pfs 8 8 2 or 3 pclkb 0008 c15ah mpc p32 pin function control register p32pfs 8 8 2 or 3 pclkb 0008 c15bh mpc p33 pin function control register p33pfs 8 8 2 or 3 pclkb 0008 c160h mpc p40 pin function control register p40pfs 8 8 2 or 3 pclkb 0008 c161h mpc p41 pin function control register p41pfs 8 8 2 or 3 pclkb 0008 c162h mpc p42 pin function control register p42pfs 8 8 2 or 3 pclkb 0008 c163h mpc p43 pin function control register p43pfs 8 8 2 or 3 pclkb 0008 c164h mpc p44 pin function control register p44pfs 8 8 2 or 3 pclkb 0008 c165h mpc p45 pin function control register p45pfs 8 8 2 or 3 pclkb 0008 c166h mpc p46 pin function control register p46pfs 8 8 2 or 3 pclkb 0008 c167h mpc p47 pin function control register p47pfs 8 8 2 or 3 pclkb 0008 c178h mpc p70 pin function control register p70pfs 8 8 2 or 3 pclkb 0008 c179h mpc p71 pin function control register p71pfs 8 8 2 or 3 pclkb 0008 c17ah mpc p72 pin function control register p72pfs 8 8 2 or 3 pclkb 0008 c17bh mpc p73 pin function control register p73pfs 8 8 2 or 3 pclkb 0008 c17ch mpc p74 pin function control register p74pfs 8 8 2 or 3 pclkb table 4.1 list of i/o register s (address order) (11 / 16) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk
r01ds0248ej0110 rev.1.10 page 36 of 98 jan 13, 2016 rx23t group 4. i/o registers 0008 c17dh mpc p75 pin function control register p75pfs 8 8 2 or 3 pclkb 0008 c17eh mpc p76 pin function control register p76pfs 8 8 2 or 3 pclkb 0008 c189h mpc p91 pin function control register p91pfs 8 8 2 or 3 pclkb 0008 c18ah mpc p92 pin function control register p92pfs 8 8 2 or 3 pclkb 0008 c18bh mpc p93 pin function control register p93pfs 8 8 2 or 3 pclkb 0008 c18ch mpc p94 pin function control register p94pfs 8 8 2 or 3 pclkb 0008 c192h mpc pa2 pin function control register pa2pfs 8 8 2 or 3 pclkb 0008 c193h mpc pa3 pin function control register pa3pfs 8 8 2 or 3 pclkb 0008 c194h mpc pa4 pin function control register pa4pfs 8 8 2 or 3 pclkb 0008 c195h mpc pa5 pin function control register pa5pfs 8 8 2 or 3 pclkb 0008 c198h mpc pb0 pin function control register pb0pfs 8 8 2 or 3 pclkb 0008 c199h mpc pb1 pin function control register pb1pfs 8 8 2 or 3 pclkb 0008 c19ah mpc pb2 pin function control register pb2pfs 8 8 2 or 3 pclkb 0008 c19bh mpc pb3 pin function control register pb3pfs 8 8 2 or 3 pclkb 0008 c19ch mpc pb4 pin function control register pb4pfs 8 8 2 or 3 pclkb 0008 c19dh mpc pb5 pin function control register pb5pfs 8 8 2 or 3 pclkb 0008 c19eh mpc pb6 pin function control register pb6pfs 8 8 2 or 3 pclkb 0008 c19fh mpc pb7 pin function control register pb7pfs 8 8 2 or 3 pclkb 0008 c1abh mpc pd3 pin function control register pd3pfs 8 8 2 or 3 pclkb 0008 c1ach mpc pd4 pin function control register pd4pfs 8 8 2 or 3 pclkb 0008 c1adh mpc pd5 pin function control register pd5pfs 8 8 2 or 3 pclkb 0008 c1aeh mpc pd6 pin function control register pd6pfs 8 8 2 or 3 pclkb 0008 c1afh mpc pd7 pin function control register pd7pfs 8 8 2 or 3 pclkb 0008 c1b2h mpc pe2 pin function control register pe2pfs 8 8 2 or 3 pclkb 0008 c290h system reset status register 0 rstsr0 8 8 4 or 5 pclkb 0008 c291h system reset status register 1 rstsr1 8 8 4 or 5 pclkb 0008 c293h system main clock oscillator forced oscillation control register mofcr 8 8 4 or 5 pclkb 0008 c297h system voltage monitoring circuit control register lvcmpcr 8 8 4 or 5 pclkb 0008 c298h system voltage detection level select register lvdlvlr 8 8 4 or 5 pclkb 0008 c29ah system voltage monitoring 1 circuit control register 0 lvd1cr0 8 8 4 or 5 pclkb 0008 c29bh system voltage monitoring 2 circuit control register 0 lvd2cr0 8 8 4 or 5 pclkb 0008 c4c0h poe input level control/status register 1 icsr1 16 8, 16 2 or 3 pclkb 0008 c4c2h poe output level control/status register 1 ocsr1 16 8, 16 2 or 3 pclkb 0008 c4c8h poe input level control/status register 3 icsr3 16 8, 16 2 or 3 pclkb 0008 c4cah poe software port output enable register spoer 8 8 2 or 3 pclkb 0008 c4cbh poe port output enable control register 1 poecr1 8 8 2 or 3 pclkb 0008 c4cch poe port output enable control register 2 poecr2 16 16 2 or 3 pclkb 0008 c4d0h poe port output enable control register 4 poecr4 16 16 2 or 3 pclkb 0008 c4d2h poe port output enable control register 5 poecr5 16 16 2 or 3 pclkb 0008 c4d6h poe input level control/status register 4 icsr4 16 8, 16 2 or 3 pclkb 0008 c4dah poe active level setting register 1 alr1 16 8, 16 2 or 3 pclkb 0008 c4dch poe input level control/status register 6 icsr6 16 16 2 or 3 pclkb 0008 c4e6h poe port output enable comparator detection flag register poecmpfr 16 16 2 or 3 pclkb 0008 c4e8h poe port output enable comparator request select register poecmpsel 16 16 2 or 3 pclkb 000a 0c80h cmpc0 comparator control register 0 cmpctl 8 8 1 or 2 pclkb 000a 0c84h cmpc0 comparator input select register 0 cmpsel0 8 8 1 or 2 pclkb 000a 0c88h cmpc0 comparator reference voltage select register 0 cmpsel1 8 8 1 or 2 pclkb 000a 0c8ch cmpc0 comparator output monitor register 0 cmpmon 8 8 1 or 2 pclkb 000a 0c90h cmpc0 comparator external output enable register 0 cmpioc 8 8 1 or 2 pclkb 000a 0ca0h cmpc1 comparator control register 1 cmpctl 8 8 1 or 2 pclkb 000a 0ca4h cmpc1 comparator input select register 1 cmpsel0 8 8 1 or 2 pclkb 000a 0ca8h cmpc1 comparator reference voltage select register 1 cmpsel1 8 8 1 or 2 pclkb table 4.1 list of i/o register s (address order) (12 / 16) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk
r01ds0248ej0110 rev.1.10 page 37 of 98 jan 13, 2016 rx23t group 4. i/o registers 000a 0cach cmpc1 comparator output monitor register 1 cmpmon 8 8 1 or 2 pclkb 000a 0cb0h cmpc1 comparator external output enable register 1 cmpioc 8 8 1 or 2 pclkb 000a 0cc0h cmpc2 comparator control register 2 cmpctl 8 8 1 or 2 pclkb 000a 0cc4h cmpc2 comparator input select register 2 cmpsel0 8 8 1 or 2 pclkb 000a 0cc8h cmpc2 comparator reference voltage select register 2 cmpsel1 8 8 1 or 2 pclkb 000a 0ccch cmpc2 comparator output monitor register 2 cmpmon 8 8 1 or 2 pclkb 000a 0cd0h cmpc2 comparator external output enable register 2 cmpioc 8 8 1 or 2 pclkb 000c 1200h mtu3 timer control register tcr 8 8, 16, 32 4 or 5 pclka 000c 1201h mtu4 timer control register tcr 8 8 4 or 5 pclka 000c 1202h mtu3 timer mode register 1 tmdr1 8 8, 16 4 or 5 pclka 000c 1203h mtu4 timer mode register 1 tmdr1 8 8 4 or 5 pclka 000c 1204h mtu3 timer i/o control register h tiorh 8 8, 16, 32 4 or 5 pclka 000c 1205h mtu3 timer i/o control register l tiorl 8 8 4 or 5 pclka 000c 1206h mtu4 timer i/o control register h tiorh 8 8, 16 4 or 5 pclka 000c 1207h mtu4 timer i/o control register l tiorl 8 8 4 or 5 pclka 000c 1208h mtu3 timer interrupt enable register tier 8 8, 16 4 or 5 pclka 000c 1209h mtu4 timer interrupt enable register tier 8 8 4 or 5 pclka 000c 120ah mtu timer output master enable register a toera 8 8 4 or 5 pclka 000c 120dh mtu timer gate control register tgcra 8 8 4 or 5 pclka 000c 120eh mtu timer output control register 1a tocr1a 8 8, 16 4 or 5 pclka 000c 120fh mtu timer output control register 2a tocr2a 8 8 4 or 5 pclka 000c 1210h mtu3 timer counter tcnt 16 16, 32 4 or 5 pclka 000c 1212h mtu4 timer counter tcnt 16 16 4 or 5 pclka 000c 1214h mtu timer cycle data register a tcdra 16 16, 32 4 or 5 pclka 000c 1216h mtu timer dead time data register a tddra 16 16 4 or 5 pclka 000c 1218h mtu3 timer general register a tgra 16 16, 32 4 or 5 pclka 000c 121ah mtu3 timer general register b tgrb 16 16 4 or 5 pclka 000c 121ch mtu4 timer general register a tgra 16 16, 32 4 or 5 pclka 000c 121eh mtu4 timer general register b tgrb 16 16 4 or 5 pclka 000c 1220h mtu timer subcounters a tcntsa 16 16, 32 4 or 5 pclka 000c 1222h mtu timer cycle buffer register a tcbra 16 16 4 or 5 pclka 000c 1224h mtu3 timer general register c tgrc 16 16, 32 4 or 5 pclka 000c 1226h mtu3 timer general register d tgrd 16 16 4 or 5 pclka 000c 1228h mtu4 timer general register c tgrc 16 16, 32 4 or 5 pclka 000c 122ah mtu4 timer general register d tgrd 16 16 4 or 5 pclka 000c 122ch mtu3 timer status register tsr 8 8, 16 4 or 5 pclka 000c 122dh mtu4 timer status register tsr 8 8 4 or 5 pclka 000c 1230h mtu timer interrupt skipping set register 1a titcr1a 8 8, 16 4 or 5 pclka 000c 1231h mtu timer interrupt skipping counters 1a titcnt1a 8 8 4 or 5 pclka 000c 1232h mtu timer buffer transfer set register a tbtera 8 8 4 or 5 pclka 000c 1234h mtu timer dead time enable register a tdera 8 8 4 or 5 pclka 000c 1236h mtu timer output level buffer register a tolbra 8 8 4 or 5 pclka 000c 1238h mtu3 timer buffer operation transfer mode register tbtm 8 8, 16 4 or 5 pclka 000c 1239h mtu4 timer buffer operation transfer mode register tbtm 8 8 4 or 5 pclka 000c 123ah mtu timer interrupt skipping mode register a titmra 8 8 4 or 5 pclka 000c 123bh mtu timer interrupt skipping set register 2a titcr2a 8 8 4 or 5 pclka 000c 123ch mtu timer interrupt skipping counters 2a titcnt2a 8 8 4 or 5 pclka 000c 1240h mtu4 timer a/d converter start request control register tadcr 16 16 4 or 5 pclka 000c 1244h mtu4 timer a/d converter start request cycle set register a tadcora 16 16, 32 4 or 5 pclka 000c 1246h mtu4 timer a/d converter start request cycle set register b tadcorb 16 16 4 or 5 pclka 000c 1248h mtu4 timer a/d converter start request cycle set buffer register a tadcobra 16 16, 32 4 or 5 pclka table 4.1 list of i/o register s (address order) (13 / 16) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk
r01ds0248ej0110 rev.1.10 page 38 of 98 jan 13, 2016 rx23t group 4. i/o registers 000c 124ah mtu4 timer a/d converter start request cycle set buffer register b tadcobrb 16 16 4 or 5 pclka 000c 124ch mtu3 timer control register 2 tcr2 8 8 4 or 5 pclka 000c 124dh mtu4 timer control register 2 tcr2 8 8 4 or 5 pclka 000c 1260h mtu timer waveform control register a twcra 8 8 4 or 5 pclka 000c 1270h mtu timer mode register 2a tmdr2a 8 8 4 or 5 pclka 000c 1272h mtu3 timer general register e tgre 16 16 4 or 5 pclka 000c 1274h mtu4 timer general register e tgre 16 16 4 or 5 pclka 000c 1276h mtu4 timer general register f tgrf 16 16 4 or 5 pclka 000c 1280h mtu timer start register a tstra 8 8, 16 4 or 5 pclka 000c 1281h mtu timer synchronous register a tsyra 8 8 4 or 5 pclka 000c 1282h mtu timer counter synchronous start register tcsystr 8 8 4 or 5 pclka 000c 1284h mtu timer read/write enable register a trwera 8 8 4 or 5 pclka 000c 1290h mtu0 noise filter control register 0 nfcr0 8 8 4 or 5 pclka 000c 1291h mtu1 noise filter control register 1 nfcr1 8 8 4 or 5 pclka 000c 1292h mtu2 noise filter control register 2 nfcr2 8 8 4 or 5 pclka 000c 1293h mtu3 noise filter control register 3 nfcr3 8 8 4 or 5 pclka 000c 1294h mtu4 noise filter control register 4 nfcr4 8 8 4 or 5 pclka 000c 1299h mtu0 noise filter control register c nfcrc 8 8 4 or 5 pclka 000c 1300h mtu0 timer control register tcr 8 8, 16, 32 4 or 5 pclka 000c 1301h mtu0 timer mode register 1 tmdr1 8 8 4 or 5 pclka 000c 1302h mtu0 timer i/o control register h tiorh 8 8, 16 4 or 5 pclka 000c 1303h mtu0 timer i/o control register l tiorl 8 8 4 or 5 pclka 000c 1304h mtu0 timer interrupt enable register tier 8 8, 16, 32 4 or 5 pclka 000c 1306h mtu0 timer counter tcnt 16 16 4 or 5 pclka 000c 1308h mtu0 timer general register a tgra 16 16, 32 4 or 5 pclka 000c 130ah mtu0 timer general register b tgrb 16 16 4 or 5 pclka 000c 130ch mtu0 timer general register c tgrc 16 16, 32 4 or 5 pclka 000c 130eh mtu0 timer general register d tgrd 16 16 4 or 5 pclka 000c 1320h mtu0 timer general register e tgre 16 16, 32 4 or 5 pclka 000c 1322h mtu0 timer general register f tgrf 16 16 4 or 5 pclka 000c 1324h mtu0 timer interrupt enable register 2 tier2 8 8, 16 4 or 5 pclka 000c 1326h mtu0 timer buffer operation transfer mode register tbtm 8 8 4 or 5 pclka 000c 1328h mtu0 timer control register 2 tcr2 8 8 4 or 5 pclka 000c 1380h mtu1 timer control register tcr 8 8, 16 4 or 5 pclka 000c 1381h mtu1 timer mode register 1 tmdr1 8 8 4 or 5 pclka 000c 1382h mtu1 timer i/o control register tior 8 8 4 or 5 pclka 000c 1384h mtu1 timer interrupt enable register tier 8 8, 16, 32 4 or 5 pclka 000c 1385h mtu1 timer status register tsr 8 8 4 or 5 pclka 000c 1386h mtu1 timer counter tcnt 16 16 4 or 5 pclka 000c 1388h mtu1 timer general register a tgra 16 16, 32 4 or 5 pclka 000c 138ah mtu1 timer general register b tgrb 16 16 4 or 5 pclka 000c 1390h mtu1 timer input capture control register ticcr 8 8 4 or 5 pclka 000c 1391h mtu1 timer mode register 3 tmdr3 8 8 4 or 5 pclka 000c 1394h mtu1 timer control register 2 tcr2 8 8 4 or 5 pclka 000c 13a0h mtu1 timer longword counter tcntlw 32 32 4 or 5 pclka 000c 13a4h mtu1 timer longword general register tgralw 32 32 4 or 5 pclka 000c 13a8h mtu1 timer longword general register tgrblw 32 32 4 or 5 pclka 000c 1400h mtu2 timer control register tcr 8 8, 16 4 or 5 pclka 000c 1401h mtu2 timer mode register 1 tmdr1 8 8 4 or 5 pclka 000c 1402h mtu2 timer i/o control register tior 8 8 4 or 5 pclka 000c 1404h mtu2 timer interrupt enable register tier 8 8, 16, 32 4 or 5 pclka table 4.1 list of i/o register s (address order) (14 / 16) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk
r01ds0248ej0110 rev.1.10 page 39 of 98 jan 13, 2016 rx23t group 4. i/o registers 000c 1405h mtu2 timer status register tsr 8 8 4 or 5 pclka 000c 1406h mtu2 timer counter tcnt 16 16 4 or 5 pclka 000c 1408h mtu2 timer general register a tgra 16 16, 32 4 or 5 pclka 000c 140ah mtu2 timer general register b tgrb 16 16 4 or 5 pclka 000c 140ch mtu2 timer control register 2 tcr2 8 8 4 or 5 pclka 000c 1480h mtu5 timer counter u tcntu 16 16, 32 4 or 5 pclka 000c 1482h mtu5 timer general register u tgru 16 16 4 or 5 pclka 000c 1484h mtu5 timer control register u tcru 8 8 4 or 5 pclka 000c 1485h mtu5 timer control register 2u tcr2u 8 8 4 or 5 pclka 000c 1486h mtu5 timer i/o control register u tioru 8 8 4 or 5 pclka 000c 1490h mtu5 timer counter v tcntv 16 16, 32 4 or 5 pclka 000c 1492h mtu5 timer general register v tgrv 16 16 4 or 5 pclka 000c 1494h mtu5 timer control register v tcrv 8 8 4 or 5 pclka 000c 1495h mtu5 timer control register 2v tcr2v 8 8 4 or 5 pclka 000c 1496h mtu5 timer i/o control register v tiorv 8 8 4 or 5 pclka 000c 14a0h mtu5 timer counter w tcntw 16 16, 32 4 or 5 pclka 000c 14a2h mtu5 timer general register w tgrw 16 16 4 or 5 pclka 000c 14a4h mtu5 timer control register w tcrw 8 8 4 or 5 pclka 000c 14a5h mtu5 timer control register 2w tcr2w 8 8 4 or 5 pclka 000c 14a6h mtu5 timer i/o control register w tiorw 8 8 4 or 5 pclka 000c 14b2h mtu5 timer interrupt enable register tier 8 8 4 or 5 pclka 000c 14b4h mtu5 timer start register tstr 8 8 4 or 5 pclka 000c 14b6h mtu5 timer compare match clear register tcntcmpclr 8 8 4 or 5 pclka 000c 1d30h mtu a/d conversion start request select register 0 tadstrgr0 8 8 4 or 5 pclka 007f c100h flash flash p/e mode control register fpmcr 8 8 2 or 3 fclk 007f c104h flash flash area select register fasr 8 8 2 or 3 fclk 007f c108h flash flash processing start address register l fsarl 16 16 2 or 3 fclk 007f c110h flash flash processing start address register h fsarh 16 16 2 or 3 fclk 007f c114h flash flash control register fcr 8 8 2 or 3 fclk 007f c118h flash flash processing end address register l fearl 16 16 2 or 3 fclk 007f c120h flash flash processing end address register h fearh 16 16 2 or 3 fclk 007f c124h flash flash reset register fresetr 8 8 2 or 3 fclk 007f c12ch flash flash status register 1 fstatr1 8 8 2 or 3 fclk 007f c130h flash flash write buffer register 0 fwb0 16 16 2 or 3 fclk 007f c138h flash flash write buffer register 1 fwb1 16 16 2 or 3 fclk 007f c140h flash flash write buffer register 2 fwb2 16 16 2 or 3 fclk 007f c144h flash flash write buffer register 3 fwb3 16 16 2 or 3 fclk 007f c180h flash protection unlock register fpr 8 8 2 or 3 fclk 007f c184h flash protection unlock status register fpsr 8 8 2 or 3 fclk 007f c1c0h flash flash start-up setting monitor register fscmr 16 16 2 or 3 fclk 007f c1c8h flash flash access window start address monitor register fawsmr 16 16 2 or 3 fclk 007f c1d0h flash flash access window end address monitor register fawemr 16 16 2 or 3 fclk 007f c1d8h flash flash initial setting register fisr 8 8 2 or 3 fclk 007f c1dch flash flash extra area control register fexcr 8 8 2 or 3 fclk 007f c1e0h flash flash error address monitor register l feaml 16 16 2 or 3 fclk 007f c1e8h flash flash error address monitor register h feamh 16 16 2 or 3 fclk 007f c1f0h flash flash status register 0 fstatr0 8 8 2 or 3 fclk 007f c350h flashcon st unique id register 0 uidr0 32 32 2 or 3 fclk 007f c354h flashcon st unique id register 1 uidr1 32 32 2 or 3 fclk 007f c358h flashcon st unique id register 2 uidr2 32 32 2 or 3 fclk table 4.1 list of i/o register s (address order) (15 / 16) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk
r01ds0248ej0110 rev.1.10 page 40 of 98 jan 13, 2016 rx23t group 4. i/o registers note 1. odd addresses cannot be accessed in 16-bit units. when a ccessing a register in 16-bit units, access the address of the t mr0 or tmr2 register. table 22.4 lists register allocation for 16-bit access in the user?s manual: hardware. 007f c35ch flashcon st unique id register 3 uidr3 32 32 2 or 3 fclk 007f ffb2h flash flash p/e mode entry register fentryr 16 16 2 or 3 fclk table 4.1 list of i/o register s (address order) (16 / 16) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk
r01ds0248ej0110 rev.1.10 page 41 of 98 jan 13, 2016 rx23t group 5. electrical characteristics 5. electrical characteristics 5.1 absolute maximum ratings caution: permanent damage to the mcu may result if absolute maximum ratings are exceeded. to preclude any malfunctions due to noise interference, insert capacitors of high frequency characteristics between the vcc and vss pins, between the avcc0 and avss0 pins, between the vrefh0 and vrefl0 pins. place capacitors of about 0.1 f as close as possible to every power supply pin and use the shortest and heaviest possible traces. connect the vcl pin to a vss pin via a 4.7 f capacitor. the capacitor must be placed close to the pin. do not input signals or an i/o pull-up power supply to ports other than 5-v tolerant ports while the device is not powered. the current injection that results from input of such a signal or i/o pull-up may cause malfunction and the abnormal current th at passes in the device at this time may cause degradation of internal elements. even if ?0.3 to +6.5 v is input to 5-v tolerant ports, it will not cause problems such as damage to the mcu. note 1. ports b1 and b2 are 5 v tolerant. note 2. the upper limit of operating temperature is 85c or 105c, depending on the product. for details, refer to section 1.2, list of products. note 1. avcc0/vrefh0 and vcc can be set individually within the operating range. note 2. when powering on the vcc and avcc0/vrefh0 pins, power th em on at the same time or the vcc pin first and then the avcc0/vrefh0 pin. table 5.1 absolute maximum ratings conditions: vss = avss0 = vrefl0 = 0 v item symbol value unit power supply voltage vcc ?0.3 to +6.5 v input voltage port 4 v in -0.3 to avcc0+0.3 v except for port 4 and ports for 5 v tolerant* 1 ?0.3 to vcc+0.3 v ports for 5 v tolerant* 1 ?0.3 to +6.5 v reference power supply voltage vrefh0 ?0.3 to avcc0+0.3 v analog power supply voltage avcc0 ?0.3 to +6.5 v analog input voltage when an000 to an007 used v an ?0.3 to avcc0+0.3 v when an016 and an017 used ?0.3 to vcc+0.3 operating temperature* 2 t opr ?40 to +85 ?40 to +105 c storage temperature t stg ?55 to +125 c table 5.2 recommended operating voltage conditions item symbol conditions min. typ. max. unit power supply voltages vcc *1, *2 2.7 ? 5.5 v vss ? 0 ? analog power supply voltages avcc0 *1, *2 vcc ? 5.5 v vrefh0 *1, *2 ?avcc0? avss0, vrefl0 ? 0 ?
r01ds0248ej0110 rev.1.10 page 42 of 98 jan 13, 2016 rx23t group 5. electrical characteristics 5.2 dc characteristics table 5.3 dc characteristics (1) conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions schmitt trigger input voltage riic input pin (except for smbus, 5 v tolerant) v ih vcc 0.7 ? 5.8 v ports b1 and b2 (5 v tolerant) vcc 0.8 ? 5.8 ports 00 to 02, 10, 11 ports 22 to 24 ports 30 to 33, 36, 37 ports 70 to 76 ports 91 to 94 ports a2 to a5 ports b0, b3 to b7 ports d3 to d7 port e2 port res# vcc 0.8 ? vcc + 0.3 ports 40 to 47 avcc0 0.8 ? avcc0 + 0.3 riic input pin (except for smbus) v il ?0.3 ? vcc 0.3 ports 40 to 47 ?0.3 ? avcc0 0.2 other than riic input pin or ports 40 to 47 ?0.3 ? vcc 0.2 riic input pin (except for smbus) ?v t vcc 0.05 ? ? ports 40 to 47 avcc0 0.1 ? ? other than riic input pin or ports 40 to 47 vcc 0.1 ? ? input level voltage (except for schmitt trigger input pins) md v ih vcc 0.9 ? vcc + 0.3 v extal (external clock input) vcc 0.8 ? vcc + 0.3 riic input pin (smbus) 2.1 ? vcc + 0.3 md v il ?0.3 ? vcc 0.1 extal (external clock input) ?0.3 ? vcc 0.2 riic input pin (smbus) ?0.3 ? 0.8 table 5.4 dc characteristics (2) conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions input leakage current res#, md, port e2 ? i in ? ??1.0 av in = 0 v, vcc three-state leakage current (off-state) port 4 ? i tsi ? ??1.0 av in = 0 v, avcc0 ports except for 5-v tolerant ports and port 4 ??0.2 v in = 0 v, vcc ports for 5 v tolerant ? ? 1.0 v in = 0 v, 5.8 v input capacitance all input pins c in ? 4 15 pf v in = 0 mv, f = 1 mhz, t a = 25c input pull-up resistor all ports (except for port e2) r u 10 20 50 k ? v in = 0 v
r01ds0248ej0110 rev.1.10 page 43 of 98 jan 13, 2016 rx23t group 5. electrical characteristics table 5.5 dc characteristics (3) conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol typ. max. unit test conditions supply current * 1 high-speed operating mode normal operating mode no peripheral operation* 2 iclk = 40 mhz i cc 4.6 ? ma iclk = 32 mhz 3.9 ? iclk = 16 mhz 2.8 ? iclk = 8 mhz 2.2 ? all peripheral operation: normal iclk = 40 mhz* 3 15.0 ? iclk = 32 mhz* 4 12.4 ? iclk = 16 mhz* 4 7.2 ? iclk = 8 mhz* 4 4.6 ? all peripheral operation: max. iclk = 40 mhz* 3 ? 33.0 iclk = 32 mhz* 4 ? 24.5 sleep mode no peripheral operation* 2 iclk = 40 mhz 2.7 ? iclk = 32 mhz 2.3 ? iclk = 16 mhz 1.9 ? iclk = 8 mhz 1.6 ? all peripheral operation: normal iclk = 40 mhz* 3 6.8 ? iclk = 32 mhz* 4 5.7 ? iclk = 16 mhz* 4 3.6 ? iclk = 8 mhz* 4 2.5 ? deep sleep mode no peripheral operation* 2 iclk = 40 mhz 1.7 ? iclk = 32 mhz 1.5 ? iclk = 16 mhz 1.3 ? iclk = 8 mhz 1.3 ? all peripheral operation: normal iclk = 40 mhz* 3 5.3 ? iclk = 32 mhz* 4 4.4 ? iclk = 16 mhz* 4 2.8 ? iclk = 8 mhz* 4 2.0 ? middle-speed operating modes normal operating mode no peripheral operation* 6 iclk = 12 mhz i cc 2.6 ? ma iclk = 8 mhz 1.9 ? iclk = 1 mhz 1.3 ? all peripheral operation: normal* 7 iclk = 12 mhz 5.5 ? iclk = 8 mhz 4.2 ? iclk = 1 mhz 1.6 ? all peripheral operation: max.* 7 iclk = 12 mhz ? 11.0
r01ds0248ej0110 rev.1.10 page 44 of 98 jan 13, 2016 rx23t group 5. electrical characteristics note 1. supply current values do not include output charge/discharge current from all pins. the values appl y when internal pull- up moss are in the off state. note 2. supply of the clock signal to peripheral modules is stopped in this state. the clock source is pll. fclk and pclk are di vision by 64. note 3. the clock signal to peripheral modules is supplied in this state. the clock source is pll. fclk is division by 2. the fr equency of pclk is same as iclk. note 4. the clock signal to peripheral modules is supplied in this state. the clock so urce is pll. the frequencies of fclk and p clk are same as iclk. note 5. values when vcc = 5 v. note 6. supply of the clock signal to peripheral modules is stopped in this state. the clock source is pll. fclk and pclk are di vision by 64. note 7. supply of the clock signal to peri pheral modules is stopped in this state. t he clock source is pll. the frequencies of f clk and pclk are same as iclk. note 1. supply current values are with all output pi ns unloaded and all input pull-up moss in the off state. note 2. the iwdt and lvd are stopped. note 3. vcc = 5 v. supply current * 1 middle-speed operating modes sleep mode no peripheral operation* 6 iclk = 12 mhz i cc 2.0 ? ma iclk = 8 mhz 1.4 ? iclk = 1 mhz 1.2 ? all peripheral operation: normal* 7 iclk = 12 mhz 2.8 ? iclk = 8 mhz 2.3 ? iclk = 1 mhz 1.3 ? deep sleep mode no peripheral operation* 6 iclk = 12 mhz 1.5 ? iclk = 8 mhz 1.2 ? iclk = 1 mhz 1.1 ? all peripheral operation: normal* 7 iclk = 12 mhz 2.8 ? iclk = 8 mhz 2.3 ? iclk = 1 mhz 1.1 ? table 5.6 dc characteristics (4) conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol typ.* 3 max. unit test conditions supply current* 1 software standby mode* 2 t a = 25c i cc 0.45 0.91 a t a = 55c 0.66 2.23 t a = 85c 1.50 9.14 t a = 105c 3.42 23.94 item symbol typ. max. unit test conditions
r01ds0248ej0110 rev.1.10 page 45 of 98 jan 13, 2016 rx23t group 5. electrical characteristics figure 5.1 voltage dependency in software standby mode (reference data) figure 5.2 temperature dependency in software standby mode (reference data) 100 10 1 0 2.0 2.5 3.0 3.5 4.0 4.5 6.0 5.0 5.5 ta = 25c *2 ta = 25c *1 ta = 55c *2 ta = 55c *1 ta = 85c *2 ta = 85c *1 ta = 105c *2 ta = 105c *1 icc ( ? a) ta = 105c *2 ta = 85c *2 ta = 105c *1 ta = 85c *1 ta = 55c *2 ta = 55c *1 ta = 25c *2 ta = 25c *1 vcc (v) note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation. average value of the tested middle samples during product evaluation. average value of the tested upper-limit samples during product evaluation. icc (?a) ta (c) 10 1 -40 0.1 100 04 08 01 2 0 -20 20 60 100
r01ds0248ej0110 rev.1.10 page 46 of 98 jan 13, 2016 rx23t group 5. electrical characteristics note: please contact a renesas electronics sales office for info rmation on the derating of the g-version product. derating is th e systematic reduction of load for t he sake of improved reliability. note 1. total power dissipated by the entire chip (including output currents) note 1. the value of the d/a converter is the value of the power supply current including the reference current. note 2. when vcc = avcc0 = 5 v. note 3. current consumed only by the comparator c module. note 1. when ofs1.lvdas = 0. note 2. turn on the power supply voltage according to the normal startup rising gradient because the register settings set by ofs1 are not read in boot mode. table 5.7 dc characteristics (5) conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol typ. max. unit test conditions permissible total consumption power* 1 pd ? 300 mw d-version product permissible total consumption power* 1 pd ? 125 mw g-version product table 5.8 dc characteristics (6) conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ.* 2 max. unit test conditions analog power supply current during a/d conversion (sampl e-and-hold circuits in use) i avcc ?3.15.2ma during a/d conversion (s ample-and-hold circuits not in use) ?0.91.8 during d/a conversion* 1 ?0.40.9 waiting for a/d and d/a conversion (all units) ? ? 0.4 a reference power supply current during a/d conversion i refh0 ? 80 130 a waiting for a/d conver sion (all units) ? ? 60 na comparator c operating current* 3 comparator enabled (per channel) i cmp ?4060 a table 5.9 dc characteristics (7) conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max . unit test conditions power-on vcc rising gradient at normal startup srvcc 0.02 ? 20 ms/v voltage monitoring 0 reset enabled at startup* 1, * 2 0.02 ? ?
r01ds0248ej0110 rev.1.10 page 47 of 98 jan 13, 2016 rx23t group 5. electrical characteristics figure 5.3 ripple waveform note: the recommended capacitance is 4.7 f. variations in connected capacitor s should be within the above range. note: do not exceed the permissible total supply current. table 5.10 dc characteristics (8) conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c the ripple voltage must meet the allowable ripple frequency f r (vcc) within the range between the vcc upper limit (5.5 v) and lower limit (2.7 v). when vcc change exceeds vcc 10%, the allowable voltage change rising/falling gradient dt/dvcc must be met. item symbol min. typ. max. unit test conditions allowable ripple frequency f r (vcc) ? ? 10 khz figure 5.3 v r (vcc) vcc 0.2 ? ? 1 mhz figure 5.3 v r (vcc) vcc 0.08 ? ? 10 mhz figure 5.3 v r (vcc) vcc 0.06 allowable voltage change rising/falling gradient dt/dvcc 1.0 ? ? ms/v when vcc change exceeds vcc 10% table 5.11 dc characteristics (9) conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions permissible error of vcl pin external capacitance c vcl 3.3 4.7 6.1 f table 5.12 permissible output currents conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol max. unit permissible output low current large current ports (ports 71 to 76, port b5, port d3) i ol 10.0 ma riic pins 6.0 ports other than above normal output mode 4.0 high-drive output mode 8.0 permissible output low current total of large current ports ? i ol 50 total of all output pins 110 permissible output high current large current ports (ports 71 to 76, port b5, port d3) i oh ?5.0 ports other than above normal output mode ?4.0 high-drive output mode ?8.0 permissible output high current total of large current ports ? i oh ?25 total of all output pins ?35 v r(vcc) vcc 1 / f r(vcc)
r01ds0248ej0110 rev.1.10 page 48 of 98 jan 13, 2016 rx23t group 5. electrical characteristics 5.2.1 normal i/o pin out put characteristics (1) figure 5.4 to figure 5.7 show the characteristics when normal output is selected by the drive capacity control register. figure 5.4 v oh /v ol and i oh /i ol voltage characteristics at t a = 25c when normal output is selected (reference data) table 5.13 output values of voltage conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. max. unit test conditions output low large current ports (ports 71 to 76, port b5, port d3) v ol ?0.8vi ol = 10.0ma riic pins standard mode ? 0.4 i ol = 3.0ma fast mode ? 0.6 i ol = 6.0ma ports other than above normal output mode ? 0.8 i ol = 1.0ma high-drive output mode ? 0.8 i ol = 2.0ma output high large current ports (ports 71 to 76, port b5, port d3) v oh vcc ? 0.8 ?vi oh = ? 5.0ma ports 40 to 47 avcc0 ? 0.8 ?i oh = ? 2.0ma ports other than above normal output mode vcc ? 0.8 ?i oh = ? 2.0ma high-drive output mode vcc ? 0.8 ?i oh = ? 4.0ma i oh /i ol vs v oh /v ol 60 40 20 0 -20 -40 -60 0.0 1.0 2.0 3.0 4.0 5.0 6.0 i oh /i ol [ma] v cc = 5.5 v v cc = 5.0 v v cc = 2.7 v v cc = 2.7 v v cc = 5.0 v v cc = 5.5 v v oh /v ol [v]
r01ds0248ej0110 rev.1.10 page 49 of 98 jan 13, 2016 rx23t group 5. electrical characteristics figure 5.5 v oh /v ol and i oh /i ol temperature characteristics at vcc = 2.7 v when normal output is selected (reference data) figure 5.6 v oh /v ol and i oh /i ol temperature characteristics at vcc = 5.0 v when normal output is selected (reference data) i oh /i ol vs v oh /v ol 20 15 5 0 -5 -15 -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 i oh /i ol [ma] ta = 25c ta = 105c v oh /v ol [v] 10 -10 ta = 25c ta = - 40c ta = 105c ta = -40c i oh /i ol vs v oh /v ol 60 40 20 0 -20 -40 -60 0.0 1.0 2.0 3.0 4.0 5.0 6.0 i oh /i ol [ma] v oh /v ol [v] ta = 25c ta = 105c ta = 25c ta = -40c ta = 105c ta = -40c
r01ds0248ej0110 rev.1.10 page 50 of 98 jan 13, 2016 rx23t group 5. electrical characteristics figure 5.7 v oh /v ol and i oh /i ol temperature characteristics at vcc = 5.5 v when normal output is selected (reference data) i oh /i ol vs v oh /v ol 60 40 20 0 -20 -40 -60 0.0 1.0 2.0 3.0 4.0 5.0 6.0 i oh /i ol [ma] v oh /v ol [v] ta = 25c ta = 105c ta = 25c ta = -40c ta = 105c ta = -40c
r01ds0248ej0110 rev.1.10 page 51 of 98 jan 13, 2016 rx23t group 5. electrical characteristics 5.2.2 standard i/o pin outp ut characteristics (2) figure 5.8 to figure 5.11 show the characteristics when high-drive ou tput is selected by the drive capacity control register. figure 5.8 v oh /v ol and i oh /i ol voltage characteristics at t a = 25c when normal output is selected (reference data) figure 5.9 v oh /v ol and i oh /i ol temperature characteristics at vcc = 2.7 v when normal output is selected (reference data) i oh /i ol vs v oh /v ol 0.0 1.0 2.0 3.0 4.0 5.0 6.0 v oh /v ol [v] 150 100 50 0 -50 -100 -150 i oh /i ol [ma] v cc = 5.5 v v cc = 5.0 v v cc = 2.7 v v cc = 2.7 v v cc = 5.0 v v cc = 5.5 v i oh /i ol vs v oh /v ol 40 30 10 0 -10 -30 -40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 i oh /i ol [ma] ta = 25c ta = 105c v oh /v ol [v] 20 -20 ta = 25c ta = -40c ta = 105c ta = -40c
r01ds0248ej0110 rev.1.10 page 52 of 98 jan 13, 2016 rx23t group 5. electrical characteristics figure 5.10 v oh /v ol and i oh /i ol temperature characteristics at vcc = 5.0 v when normal output is selected (reference data) figure 5.11 v oh /v ol and i oh /i ol temperature characteristics at vcc = 5.5 v when normal output is selected (reference data) i oh /i ol vs v oh /v ol 150 100 50 0 -50 -100 -150 0.0 1.0 2.0 3.0 4.0 5.0 6.0 i oh /i ol [ma] v oh /v ol [v] ta = 25c ta = 105c ta = 25c ta = -40c ta = 105c ta = -40c i oh /i ol vs v oh /v ol 150 100 50 0 -50 -100 -150 0.0 1.0 2.0 3.0 4.0 5.0 6.0 i oh /i ol [ma] v oh /v ol [v] ta = 25c ta = 105c ta = 25c ta = -40c ta = 105c ta = -40c
r01ds0248ej0110 rev.1.10 page 53 of 98 jan 13, 2016 rx23t group 5. electrical characteristics 5.2.3 standard i/o pin outp ut characteristics (3) figure 5.12 to figure 5.15 show the output characteristics of the large curr ent ports (ports 71 to 76, port b5, port d3). figure 5.12 v oh /v ol and i oh /i ol voltage characteristics of large current ports (ports 71 to 76, port b5, port d3) at t a = 25c (reference data) figure 5.13 v oh /v ol and i oh /i ol temperature characteristics of large current ports (ports 71 to 76, port b5, port d3) at vcc = 2.7 v (reference data) i oh /i ol vs v oh /v ol 250 150 100 0 -100 -150 -250 0.0 1.0 2.0 3.0 4.0 5.0 6.0 i oh /i ol [ma] v cc = 5.5 v v cc = 5.0 v v cc = 2.7 v v cc = 2.7 v v cc = 5.0 v v cc = 5.5 v v oh /v ol [v] 200 50 -50 -200 i oh /i ol vs v oh /v ol 60 40 20 0 -20 -40 -60 0.0 0.5 1.0 1.5 2.0 2.5 3.0 i oh /i ol [ma] ta = 25c ta = 105c v oh /v ol [v] ta = 25c ta = -40c ta = 105c ta = -40c
r01ds0248ej0110 rev.1.10 page 54 of 98 jan 13, 2016 rx23t group 5. electrical characteristics figure 5.14 v oh /v ol and i oh /i ol temperature characteristics of large current ports (ports 71 to 76, port b5, port d3) at vcc = 5.0 v (reference data) figure 5.15 v oh /v ol and i oh /i ol temperature characteristics of large current ports (ports 71 to 76, port b5, port d3) at vcc = 5.5 v (reference data) 5.2.4 riic pin output characteristics figure 5.16 to figure 5.19 show the output characteristics of the riic pin. i oh /i ol vs v oh /v ol 250 150 100 0 -100 -150 -250 0.0 1.0 2.0 3.0 4.0 5.0 6.0 i oh /i ol [ma] v oh /v ol [v] ta = 25c ta = 105c ta = 25c ta = -40c ta = 105c ta = -40c 200 50 -50 -200 i oh /i ol vs v oh /v ol 250 150 100 0 -100 -150 -250 0.0 1.0 2.0 3.0 4.0 5.0 6.0 i oh /i ol [ma] v oh /v ol [v] ta = 25c ta = 105c ta = 25c ta = -40c ta = 105c ta = -40c 200 50 -50 -200
r01ds0248ej0110 rev.1.10 page 55 of 98 jan 13, 2016 rx23t group 5. electrical characteristics figure 5.16 v ol and i ol voltage characteristics of riic output pin at t a = 25c (reference data) figure 5.17 v ol and i ol temperature characteristics of riic outp ut pin at vcc = 2.7 v (reference data) i ol vs v ol 150 100 50 0 -50 -100 -150 0.0 1.0 2.0 3.0 4.0 5.0 6.0 i ol [ma] v cc = 5.5 v v cc = 5.0 v v cc = 2.7 v v ol [v] i ol vs v ol 40 30 10 0 -10 -30 -40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 i ol [ma] ta = 25c v ol [v] 20 -20 ta = 105c ta = -40c
r01ds0248ej0110 rev.1.10 page 56 of 98 jan 13, 2016 rx23t group 5. electrical characteristics figure 5.18 v ol and i ol temperature characteristics of riic outp ut pin at vcc = 5.0 v (reference data) figure 5.19 v ol and i ol temperature characteristics of riic outp ut pin at vcc = 5.5 v (reference data) i ol vs v ol 150 100 50 0 -50 -100 -150 0.0 1.0 2.0 3.0 4.0 5.0 6.0 i ol [ma] v ol [v] ta = 25c ta = 105c ta = -40c i ol vs v ol 150 100 50 0 -50 -100 -150 0.0 1.0 2.0 3.0 4.0 5.0 6.0 i ol [ma] v ol [v] ta = 25c ta = 105c ta = -40c
r01ds0248ej0110 rev.1.10 page 57 of 98 jan 13, 2016 rx23t group 5. electrical characteristics 5.3 ac characteristics 5.3.1 clock timing note 1. the lower-limit frequency of fclk is 1 mhz during programming or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note 2. the frequency accuracy of fclk should be 3.5%. note 1. the lower-limit frequency of fclk is 1 mhz during programming or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note 2. the frequency accuracy of fclk should be 3.5%. table 5.14 operating frequency value (high-speed operating mode) conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit maximum operating frequency system clock (iclk) f max ??4 0m h z flashif clock (fclk)* 1, * 2 ??3 2 peripheral module clock (pclka) ? ? 40 peripheral module clock (pclkb) ? ? 40 peripheral module clock (pclkd) ? ? 40 table 5.15 operating frequency value (middle-speed operating mode) conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit maximum operating frequency system clock (iclk) f max ??1 2m h z flashif clock (fclk)* 1, * 2 ??1 2 peripheral module clock (pclka) ? ? 12 peripheral module clock (pclkb) ? ? 12 peripheral module clock (pclkd) ? ? 12
r01ds0248ej0110 rev.1.10 page 58 of 98 jan 13, 2016 rx23t group 5. electrical characteristics note 1. time until the clock can be used afte r the main clock oscillator stop bit (mosccr.mostp) is set to 0 (operating) when th e external clock is stable. note 2. reference values when an 8-mhz resonator is used. when specifying the main clock oscillator st abilization time, set the moscwtcr register with a stabilization time value that is equal to or greater than the resonator-manufacturer-recommended value. after changing the setting of the mosccr.mostp bit so that the main clock oscillator operates, read the oscovfsr.moovf flag to confirm that is has become 1, and then start using the main clock. figure 5.20 extal external clock input timing table 5.16 clock timing conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions extal external clock input cycle time t xcyc 50 ? ? ns figure 5.20 extal external clock input high pulse width t xh 20 ? ? ns extal external clock input low pulse width t xl 20 ? ? ns extal external clock rise time t xr ?? 5 ns extal external clock fall time t xf ?? 5 ns extal external clock input wait time * 1 t exwt 0.5 ? ? s main clock oscillator oscillation frequency * 2 f main 1?20mhz main clock oscillation stabilization time (crystal) * 2 t mainosc ? 3 ? ms figure 5.21 main clock oscillation st abilization time (ceramic resonator) * 2 t mainosc ?50? s loco clock oscillation frequency f loco 3.44 4.0 4.56 mhz loco clock oscillati on stabilization time t loco ??0.5 s figure 5.22 iwdt-dedicated clock oscillation frequency f iloco 12.75 15 17.25 khz iwdt-dedicated clock oscilla tion stabilization time t iloco ??50 s figure 5.23 hoco clock oscillation frequency f hoco 31.52 32 32.48 mhz t a = ?40 to +85c 31.68 32 32.32 t a = ?20 to +85c 31.36 32 32.64 t a = ?40 to +105c hoco clock oscillati on stabilization time t hoco ??30 s figure 5.25 pll circuit oscillation frequency f pll 24 ? 40 mhz pll clock oscillation stabilization time t pll ??50 s figure 5.26 pll free-running oscillation frequency f pllfr ?8?mhz t xh t xcyc extal external clock input vcc 0.5 t xl t xr t xf
r01ds0248ej0110 rev.1.10 page 59 of 98 jan 13, 2016 rx23t group 5. electrical characteristics figure 5.21 main clock oscillation start timing figure 5.22 loco clock oscillation start timing figure 5.23 iwdt-dedicated cl ock oscillation start timing figure 5.24 hoco clock osci llation start timing (after reset is canceled by setting ofs1.hocoen bit to 0) main clock oscillator output mosccr.mostp t mainosc loco clock oscillator output lococr.lcstp t loco iwdt-dedicated clock oscillator output ilococr.ilcstp t iloco res# internal reset hoco clock ofs1.hocoen t reswt
r01ds0248ej0110 rev.1.10 page 60 of 98 jan 13, 2016 rx23t group 5. electrical characteristics figure 5.25 hoco clock os cillation start timing (oscillation is started by setting hococr.hcstp bit) figure 5.26 pll clock oscillation start timing (pll is operated after main cloc k oscillation has settled) hoco clock hococr.hcstp t hoco pllcr2.pllen pll clock mosccr.mostp t mainosc main clock oscillator output t pll
r01ds0248ej0110 rev.1.10 page 61 of 98 jan 13, 2016 rx23t group 5. electrical characteristics 5.3.2 reset timing note 1. when iwdtcr.cks[3:0] = 0000b. figure 5.27 reset input timing at power-on figure 5.28 reset input timing (1) figure 5.29 reset input timing (2) table 5.17 reset timing conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions res# pulse width at power-on t reswp 3 ? ? ms figure 5.27 other than above t resw 30 ? ? s figure 5.28 wait time after res# cancellation (at power-on) t reswt ? 27.5 ? ms figure 5.27 wait time after res# cancellation (during powered-on state) t reswt ?114? s figure 5.28 independent watchdog timer reset period t reswiw ? 1 ? iwdt clock cycle figure 5.29 software reset period t reswsw ? 1 ? iclk cycle wait time after independent watchdog timer reset cancellation* 1 t resw2 ? 300 ? s wait time after software reset cancellation t resw2 ? 168 ? s vcc res# t reswp internal reset t reswt res# internal reset t reswt t resw independent watchdog timer reset software reset internal reset t reswt2 t reswiw, t reswsw
r01ds0248ej0110 rev.1.10 page 62 of 98 jan 13, 2016 rx23t group 5. electrical characteristics 5.3.3 timing of recovery from low power consumption modes note 1. the recovery time varies depending on the state of each osci llator when the wait instructi on is executed. the recovery t ime when multiple oscillators are operating varies depending on the operat ing state of the oscillators that are not selected as the system clock source. the above table applies when only the corresponding clock is operating. note 2. when the frequency of crystal is 20 mhz. when the main clock oscillator wait cont rol register (moscwtcr) is set to 04h. note 3. when the frequency of the external clock is 20 mhz. when the main clock oscillator wait cont rol register (moscwtcr) is set to 00h. note 4. when the frequency of pll is 40 mhz. when the main clock oscillator wait cont rol register (moscwtcr) is set to 00h. note 1. the recovery time varies depending on the state of each osci llator when the wait instructi on is executed. the recovery t ime when multiple oscillators are operating varies depending on the operat ing state of the oscillators that are not selected as the system clock source. the above table applies when only the corresponding clock is operating. note 2. when the frequency of the crystal is 12 mhz. when the main clock oscillator wait cont rol register (moscwtcr) is set to 04h. note 3. when the frequency of the external clock is 12 mhz. when the main clock oscillator wait cont rol register (moscwtcr) is set to 00h. note 4. when the frequency of pll is 12 mhz. when the main clock oscillator wait cont rol register (moscwtcr) is set to 00h. table 5.18 timing of recovery from low power consumption modes (1) conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions recovery time from software standby mode* 1 high-speed mode crystal connected to main clock oscillator main clock oscillator operating* 2 t sbymc ? 2 3 ms figure 5.30 external clock input to main clock oscillator main clock oscillator operating* 3 t sbyex ?3550 s main clock oscillator and pll circuit operating* 4 t sbype ?7095 s loco clock oscillator operating t sbylo ?4055 s table 5.19 timing of recovery from low power consumption modes (2) conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions recovery time from software standby mode* 1 middle-speed mode crystal connected to main clock oscillator main clock oscillator operating* 2 t sbymc ? 2 3 ms figure 5.30 external clock input to main clock oscillator main clock oscillator operating* 3 t sbyex ?3 4 s main clock oscillator and pll circuit operating* 4 t sbype ?6585 s loco clock oscillator operating t sbylo ?5 7 s
r01ds0248ej0110 rev.1.10 page 63 of 98 jan 13, 2016 rx23t group 5. electrical characteristics figure 5.30 software standby mode recovery timing note 1. oscillators continue oscillating in deep sleep mode. note 2. when the frequency of the system clock is 32 mhz. note 3. when the frequency of the system clock is 12 mhz. figure 5.31 deep sleep mode recovery timing note: values when the frequencies of pclkb, pclkd, and fclk are not divided. table 5.20 timing of recovery from low power consumption modes (3) conditions: vcc = 2.7 v to avcc0, av cc0 = vrefh0 = 2.7 v to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions recovery time from deep sleep mode* 1 high-speed mode* 2 t dslp ?23.5 s figure 5.31 middle-speed mode* 3 t dslp ?3 4 s table 5.21 operating mode transition time conditions: vcc = 2.7 v to avcc0, av cc0 = vrefh0 = 2.7 v to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c mode before transition mode after transition iclk frequency transition time unit min. typ. max. high-speed operating mode middle-speed operating modes 8 mhz ? 10 ? s middle-speed operating modes high-speed operating mode 8 mhz ? 37.5 ? s oscillator iclk irq software standby mode t sbymc, t sbypc, t sbyex, t sbype, t sbysc, t sbyho, t sbylo oscillator iclk irq deep sleep mode t dslp
r01ds0248ej0110 rev.1.10 page 64 of 98 jan 13, 2016 rx23t group 5. electrical characteristics 5.3.4 control signal timing note: 200 ns minimum in software standby mode. note 1. t pcyc indicates the cycle of pclkb. note 2. t nmick indicates the cycle of the nmi digital filter sampling clock. note 3. t irqck indicates the cycle of th e irqi digital filter samp ling clock (i = 0 to 5). figure 5.32 nmi interrupt input timing figure 5.33 irq interrupt input timing table 5.22 control signal timing conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions nmi pulse width t nmiw 200 ? ? ns nmi digital filter disabled (nmiflte.nflten = 0) t pcyc 2 200 ns t pcyc 2* 1 ?? t pcyc 2 > 200 ns 200 ? ? nmi digital filter enabled (nmiflte.nflten = 1) t nmick 3 200 ns t nmick 3.5* 2 ?? t nmick 3 > 200 ns irq pulse width t irqw 200 ? ? ns irq digital filter disabled (irqflte0.flteni = 0) t pcyc 2 200 ns t pcyc 2* 1 ?? t pcyc 2 > 200 ns 200 ? ? irq digital filter enabled (irqflte0.flteni = 1) t irqck 3 200 ns t irqck 3.5* 3 ?? t irqck 3 > 200 ns nmi t nmiw irq t irqw
r01ds0248ej0110 rev.1.10 page 65 of 98 jan 13, 2016 rx23t group 5. electrical characteristics 5.3.5 timing of on-chi p peripheral modules note 1. t pcyc : pclk cycle, t pacyc : pclka cycle note 2. t cac : cac count clock source cycle table 5.23 timing of on-chip peripheral modules (1) conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. max. unit *1 test conditions i/o ports input data pulse width t prw 1.5 ? t pcyc figure 5.34 mtu3 input capture input pulse width single-edge setting t ticw 3?t pacyc figure 5.35 both-edge setting 5 ? timer clock pulse width single-edge setting t tckwh, t tckwl 3?t pacyc figure 5.36 both-edge setting 5 ? phase counting mode 5 ? poe3 poe# input pulse width t poew 1.5 ? t pcyc figure 5.37 tmr timer clock pulse width single-edge setting t tmcwh , t tmcwl 1.5 ? t pcyc figure 5.38 both-edge setting 2.5 ? sci input clock cycle asynchronous t scyc 4?t pcyc figure 5.39 clock synchronous 6 ? input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ?20ns input clock fall time t sckf ?20ns output clock cycle asynchronous t scyc 16 ? t pcyc figure 5.40 clock synchronous 4 ? output clock pulse width t sckw 0.4 0.6 t scyc output clock rise time t sckr ?20ns output clock fall time t sckf ?20ns transmit data delay time (master) clock synchronous t txd ?40ns transmit data delay time (slave) clock synchronous vcc = 4.0 v or above ? 40 ns vcc = 2.7 v or above ? 65 ns receive data setup time (master) clock synchronous vcc = 4.0 v or above t rxs 40 ? ns vcc = 2.7 v or above 65 ? ns receive data setup time (slave) clock synchronous 40 ? ns receive data hold time clock synchronous t rxh 40 ? ns a/d converter trigger input pulse width t trgw 1.5 ? t pcyc figure 5.41 cac cacref input pulse width t pcyc t cac *2 t cacref 4.5 t cac + 3 t pcyc ?ns t pcyc > t cac *2 5 t cac + 6.5 t pcyc
r01ds0248ej0110 rev.1.10 page 66 of 98 jan 13, 2016 rx23t group 5. electrical characteristics note 1. t pcyc : pclk cycle note 2. n: an integer from 1 to 8 that can be set by the rspi clock delay register (spckd) note 3. n: an integer from 1 to 8 that can be set by the rspi slave select negation delay register (sslnd) table 5.24 timing of on-chip peripheral modules (2) conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c, c = 30pf item symbol min. max. unit test conditions rspi rspck clock cycle master t spcyc 2 4096 t pcyc * 1 figure 5.42 slave 8 4096 rspck clock high pulse width master vcc = 4.0 v or above t spckwh (t spcyc ? t spckr ? t spckf )/2 ? 5 ?ns vcc = 2.7 v or above (t spcyc ? t spckr ? t spckf )/2 ? 8 ? slave (t spcyc ? t spckr ? t spckf )/2 ? rspck clock low pulse width master vcc = 4.0 v or above t spckwl (t spcyc ? t spckr ? t spckf )/2 ? 5 ?ns vcc = 2.7 v or above (t spcyc ? t spckr ? t spckf )/2 ? 8 ? slave (t spcyc ? t spckr ? t spckf )/2 ? rspck clock rise/fall time output vcc = 4.0 v or above t spckr, t spckf ?6n s vcc = 2.7 v or above ? 10 input ? 0.1 s/v data input setup time master vcc = 4.0 v or above t su 10 ? ns figure 5.43 to figure 5.46 vcc = 2.7 v or above 26 ? slave 25 ? t pcyc ? data input hold time master rspck set to a division ratio other than pclkb divided by 2 t h t pcyc ?ns rspck set to pclkb divided by 2 t hf 0? slave t h 20 + 2 t pcyc ? ssl setup time master t lead ?30 + n* 2 t spcyc ?ns slave 2 ? t pcyc ssl hold time master t lag ?30 + n* 3 t spcyc ?ns slave 2 ? t pcyc data output delay time master vcc = 4.0 v or above t od ?1 0n s vcc = 2.7 v or above ? 14 slave ? 3 t pcyc + 65 data output hold time master 2.7 v or above t oh 0?n s slave 0 ? successive transmission delay time master t td t spcyc + 2 t pcyc 8 t spcyc + 2 t pcyc ns slave 4 t pcyc ? mosi and miso rise/fall time output t dr, t df ?1 0n s input ? 1 s ssl rise/fall time output t sslr, t sslf ?1 0n s input ? 1 s slave access time t sa ?6t pcyc figure 5.45, figure 5.46 slave output release time t rel ?5t pcyc
r01ds0248ej0110 rev.1.10 page 67 of 98 jan 13, 2016 rx23t group 5. electrical characteristics note 1. t pcyc : pclk cycle table 5.25 timing of on-chip peripheral modules (3) conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c, c = 30pf item symbol min. max. unit* 1 test conditions simple spi sck clock cycle output (master) t spcyc 4 65536 t pcyc figure 5.42 sck clock cycle input (slave) 6 65536 t pcyc sck clock high pulse width t spckwh 0.4 0.6 t spcyc sck clock low pulse width t spckwl 0.4 0.6 t spcyc sck clock rise/fall time t spckr, t spckf ?20ns data input setup time (master) vcc = 4.0 v or above t su 40 ? ns figure 5.43, figure 5.44 vcc = 2.7 v or above 65 ? data input setup time (slave) 40 ? data input hold time t h 40 ? ns ss input setup time t lead 3?t spcyc ss input hold time t lag 3?t spcyc data output delay time (master) t od ?40ns data output delay time (slave) vcc = 4.0 v or above ?40 vcc = 2.7 v or above ?65 data output hold time (master) master t oh ?10 ? ns slave ?10 ? data rise/fall time t dr , t df ?20ns ss input rise/fall time t sslr , t sslf ?20ns slave access time t sa ?6t pcyc figure 5.45, figure 5.46 slave output release time t rel ?6t pcyc
r01ds0248ej0110 rev.1.10 page 68 of 98 jan 13, 2016 rx23t group 5. electrical characteristics note 1. t iiccyc : riic internal reference count clock (iic ) cycle note 2. the value in parentheses is used when the icmr3.nf[1:0] bi ts are set to 11b while a digital filter is enabled with the i cfer.nfe bit = 1. table 5.26 timing of on-chip peripheral modules (4) conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min.* 1, * 2 max. unit test conditions riic (standard mode, smbus) scl cycle time t scl 6 (12) t iiccyc + 1300 ? ns figure 5.47 scl high pulse width t sclh 3 (6) t iiccyc + 300 ? ns scl low pulse width t scll 3 (6) t iiccyc + 300 ? ns scl, sda rise time t sr ? 1000 ns scl, sda fall time t sf ? 300 ns scl, sda spike pulse removal time t sp 01 ( 4 ) t iiccyc ns sda bus free time t buf 3 (6) t iiccyc + 300 ? ns start condition hold time t stah t iiccyc + 300 ? ns repeated start condition setup time t stas 1000 ? ns stop condition setup time t stos 1000 ? ns data setup time t sdas t iiccyc + 50 ? ns data hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf riic (fast mode) scl cycle time t scl 6 (12) t iiccyc + 600 ? ns figure 5.47 scl high pulse width t sclh 3 (6) t iiccyc + 300 ? ns scl low pulse width t scll 3 (6) t iiccyc + 300 ? ns scl, sda rise time t sr ? 300 ns scl, sda fall time t sf ? 300 ns scl, sda spike pulse removal time t sp 01 ( 4 ) t iiccyc ns sda bus free time t buf 3 (6) t iiccyc + 300 ? ns start condition hold time t stah t iiccyc + 300 ? ns repeated start condition setup time t stas 300 ? ns stop condition setup time t stos 300 ? ns data setup time t sdas t iiccyc + 50 ? ns data hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf
r01ds0248ej0110 rev.1.10 page 69 of 98 jan 13, 2016 rx23t group 5. electrical characteristics note 1. t pcyc : pclk cycle note 2. c b is the total capacitance of the bus lines. figure 5.34 i/o port input timing figure 5.35 mtu3 input/output timing table 5.27 timing of on-chip peripheral modules (5) conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min.* 2 max. unit test conditions simple i 2 c (standard mode) sda rise time t sr ? 1000 ns figure 5.47 sda fall time t sf ? 300 ns sda spike pulse removal time t sp 04 t pcyc * 1 ns data setup time t sdas 250 ? ns data hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf simple i 2 c (fast mode) sda rise time t sr ? 300 ns figure 5.47 sda fall time t sf ? 300 ns sda spike pulse removal time t sp 04 t pcyc * 1 ns data setup time t sdas 100 ? ns data hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf port pclk t prw output compare output input capture input pclka t ticw
r01ds0248ej0110 rev.1.10 page 70 of 98 jan 13, 2016 rx23t group 5. electrical characteristics figure 5.36 mtu3 clock input timing figure 5.37 poe# input timing figure 5.38 tmr clock input timing figure 5.39 sck clock input timing mtclka to mtclkd pclka t tckwl t tckwh poen# input pclk t poew pclk tmci0 to tmci3 t tmcwl t tmcwh t sckw t sckr t sckf t scyc sckn n = 1, 5
r01ds0248ej0110 rev.1.10 page 71 of 98 jan 13, 2016 rx23t group 5. electrical characteristics figure 5.40 sci input/output timing: clock synchronous mode figure 5.41 a/d converter external trigger input timing t txd t rxs t rxh txdn rxdn sckn n = 1, 5 adtrg0# pclk t trgw
r01ds0248ej0110 rev.1.10 page 72 of 98 jan 13, 2016 rx23t group 5. electrical characteristics figure 5.42 rspi clock timing and simple spi clock timing figure 5.43 rspi timing (master, cpha = 0) and simple spi clock timing (master, ckph = 1) t spckwh v oh v oh v ol v ol v oh v oh t spckwl t spckr t spckf v ol t spcyc t spckwh v ih v ih v il v il v ih v ih t spckwl t spckr t spckf v il t spcyc v oh = 0.7 vcc, v ol = 0.3 vcc, v ih = 0.7 vcc, v il = 0.3 vcc n = 1, 5 sckn master select output sckn slave select input rspcka master select output rspcka slave select input simple spi rspi t dr, t df t su t h t lead t td t lag t sslr, t sslf t oh t od msb in data lsb in msb in msb out data lsb out idle msb out sckn ckpol = 0 output sckn ckpol = 1 output smison input smosin output n = 1, 5 simple spi rspi ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output
r01ds0248ej0110 rev.1.10 page 73 of 98 jan 13, 2016 rx23t group 5. electrical characteristics figure 5.44 rspi timing (master, cpha = 1) and simple spi clock timing (master, ckph = 0) figure 5.45 rspi timing (sl ave, cpha = 0) and simple spi clock timing (slave, ckph = 1) ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output rspi simple spi sckn ckpol = 1 output sckn ckpol = 0 output smison input smosin output t dr, t df t su t h t lead t td t lag t sslr, t sslf t oh msb in data lsb in msb in msb out data lsb out idle msb out t od n = 1, 5 t dr, t df t su t h t lead t td t lag t sa msb in data lsb in msb msb out data lsb out msb in msb t oh t od t rel sckn ckpol = 0 input sckn ckpol = 1 input smison output smosin input n = 1, 5 simple spi rspi ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input ssn# input
r01ds0248ej0110 rev.1.10 page 74 of 98 jan 13, 2016 rx23t group 5. electrical characteristics figure 5.46 rspi timing (sl ave, cpha = 1) and simple spi clock timing (slave, ckph = 0) figure 5.47 riic bus interface input/output timing and simple i 2 c bus interface input/output timing t dr, t df t sa t oh t lead t td t lag t h lsb out (last data) data msb out msb in data lsb in msb in lsb out t su t od t rel msb out sckn ckpol = 1 input sckn ckpol = 0 input smison output smosin input n = 1, 5 simple spi rspi ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input ssn# input test conditions v ih = vcc 0.7, v il = vcc 0.3 sda scl v ih v il t stah t sclh t scll p *1 s *1 t sf t sr t scl t sdah t sdas t stas t sp t stos p *1 t buf sr *1 note 1. s, p, and sr indicate the following conditions, respectively. s: start condition p: stop condition sr: repeated start condition
r01ds0248ej0110 rev.1.10 page 75 of 98 jan 13, 2016 rx23t group 5. electrical characteristics 5.4 a/d conversion characteristics note: the characteristics apply when no pin functions other than a/d converter input are used. absolute accuracy includes quantization errors. offset error, full-scale error, dnl diffe rential nonlinearity error, and inl integral nonlinearity error d o not include quantization errors. note 1. the conversion time is the sum of the sampling time a nd the comparison time. as the test conditions, the number of sampl ing states is indicated. table 5.28 a/d conversion characteristics (1) conditions: vcc = 4.5 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item min. typ. max. unit test conditions frequency 1 ? 40 mhz resolution ? ? 12 bit conversion time* 1 (operation at pclkd = 40 mhz) permissible signal source impedance (max.) = 1.0 k ? sample-and-hold circuit not in use 1.00 ? ? s high-precision channel adsstrn.sst[7:0] bits = 08h 1.25 ? ? s normal-precision channel adsstrn.sst[7:0] bits = 12h permissible signal source impedance (max.) = 1.0 k ? / sample-and-hold circuit in use 1.65 ? ? s high-precision channel adsstrn.sst[7:0] bits = 08h adshcr.sstsh[7:0] bits = 0dh an000 to an002 = 0.25 v to vrefh0 ? 0.25 v analog input capacitance ? ? 12 pf offset error ? ? 6.5 lsb full-scale error ? ? 6.5 lsb quantization error ? 0.5 ? lsb absolute accuracy ? ? 8.0 lsb dnl differential nonlinearity error ? 0.5 1.5 lsb inl integral nonlinearity error ? 2.0 4.0 lsb
r01ds0248ej0110 rev.1.10 page 76 of 98 jan 13, 2016 rx23t group 5. electrical characteristics note: the characteristics apply when no pin functions other than a/d converter input are used. absolute accuracy includes quantization errors. offset error, full-scale error, dnl diffe rential nonlinearity error, and inl integral nonlinearity error d o not include quantization errors. note 1. the conversion time is the sum of the sampling time a nd the comparison time. as the test conditions, the number of sampl ing states is indicated. note 1. the a/d internal reference voltage indicates the voltage wh en the internal reference voltage is input to the a/d convert er. table 5.29 a/d conversion characteristics (2) conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item min. typ. max. unit test conditions frequency 1 ? 40 mhz resolution ? ? 12 bit conversion time* 1 (operation at pclkd = 40 mhz) permissible signal source impedance (max.) = 1.0 k ? sample-and-hold circuit not in use 1.15 ? ? s high-precision channel adsstrn.sst[7:0] bits = 0eh 1.30 ? ? s normal-precision channel adsstrn.sst[7:0] bits = 14h permissible signal source impedance (max.) = 1.0 k ? sample-and-hold circuit in use 1.90 ? ? s high-precision channel adsstrn.sst[7:0] bits = 0eh adshcr.sstsh[7:0] bits = 11h an000 to an002 = 0.25 v to vrefh0 ? 0.25 v analog input capacitance ? ? 12 pf offset error ? ? 6.5 lsb full-scale error ? ? 6.5 lsb quantization error ? 0.5 ? lsb absolute accuracy ? ? 8.0 lsb dnl differential nonlinearity error ? 0.5 1.5 lsb inl integral nonlinearity error ? 2.0 4.0 lsb table 5.30 a/d converter channel classification classification channel conditions remarks high-precision channel an000 to an007 avcc0 = 2.7 to 5.5 v pins an000 to an007 cannot be used as digital outputs when the a/d converter is in use. normal-precision channel an016, an017 vcc = avcc0 = 2.7 to 5.5 v internal reference voltage input channel internal reference voltage avcc0 = 2.7 to 5.5 v table 5.31 a/d internal reference voltage characteristics conditions: vcc = 2.7 v to avcc0, av cc0 = vrefh0 = 2.7 v to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item min. typ. max. unit test conditions internal reference voltage input channel* 1 1.36 1.43 1.50 v
r01ds0248ej0110 rev.1.10 page 77 of 98 jan 13, 2016 rx23t group 5. electrical characteristics figure 5.48 illustration of a/d converter characteristic terms absolute accuracy absolute accuracy is the difference between output code based on the theoretical a/d conversion characteristics, and the actual a/d conversion result. when measur ing absolute accuracy, the voltage at th e midpoint of the width of analog input voltage (1-lsb width), that can m eet the expectation of outp utting an equal code based on the theoretical a/d conversion characteristics, is us ed as an analog input voltage. for example, if 12-bit resolution is used and if reference voltage (vrefh0 = 3.072 v), then 1-lsb width becomes 0.75 mv, and 0 mv, 0.75 mv, 1.5 mv, ... are used as analog input voltages. if analog input voltage is 6 mv, absolute accuracy = 5 lsb means that the actual a/d conversion result is in the range of 003h to 00dh though an output code, 008h, can be expect ed from the theoretical a/d conversion characteristics. integral nonlinearity error (inl) integral nonlinearity error is the maximum deviation between the ideal line when the meas ured offset and full-scale errors are zeroed, and the actual output code. integral nonlinearity error (inl) actual a/d conversion characteristic ideal a/d conversion characteristic analog input voltage offset error absolute accuracy differential nonlinearity error (dnl) full-scale error fffh 000h 0 ideal line of actual a/d conversion characteristic 1-lsb width for ideal a/d conversion characteristic differential nonlinearity error (dnl) 1-lsb width for ideal a/d conversion characteristic vrefh0 (full-scale) a/d converter output code
r01ds0248ej0110 rev.1.10 page 78 of 98 jan 13, 2016 rx23t group 5. electrical characteristics differential nonlinearity error (dnl) differential nonlinearity error is the difference between 1-lsb width base d on the ideal a/d conver sion characteristics and the width of the actual output code. offset error offset error is the difference between a transition point of the ideal first output code and the actual first output code. full-scale error full-scale error is the differen ce between a transition point of the ideal last output code and the actual last output code.
r01ds0248ej0110 rev.1.10 page 79 of 98 jan 13, 2016 rx23t group 5. electrical characteristics 5.5 comparator characteristics figure 5.49 comparator response time table 5.32 comparator characteristics conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions offset voltage v cioff ??40mv reference input voltage range v cref 0?avcc0v response time t cr ? ? 200 ns vod = 100 mv cmpctl.cdfs = 0 t cf ? ? 200 ns stabilization wait time for input selection t cwait 300 ? ? ns operation stabilization wait time t cmp ?1 s cvrefn an000 to an007 comp0 to comp2 (n = 0, 1) 100 mv 100 mv t cr t cf
r01ds0248ej0110 rev.1.10 page 80 of 98 jan 13, 2016 rx23t group 5. electrical characteristics 5.6 d/a conversion characteristics table 5.33 d/a conversion characteristics conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions resolution ? ? ? 8 bit conversion time t dconv ??3 . 0 s absolute accuracy ? ? 1.0 3.0 lsb
r01ds0248ej0110 rev.1.10 page 81 of 98 jan 13, 2016 rx23t group 5. electrical characteristics 5.7 power-on reset circuit and voltage detection circuit characteristics note: these characteristics apply when noise is not superimposed on the power supply. wh en a setting is made so that the voltage detection level overlaps with that of the voltage detection circ uit (lvd2), it cannot be specified which of lvd1 and lvd2 is us ed for voltage detection. note 1. n in the symbol vdet0_n denotes the value of the lvds0[1:0] bits. note 2. n in the symbol vdet1_n denotes the value of the lvdlvlr.lvd1lvl[3:0] bits. note 3. n in the symbol vdet2_n denotes the value of the lvdlvlr.lvd2lvl[3:0] bits. table 5.34 power-on reset circuit and volt age detection circuit characteristics (1) conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions voltage detection level power-on reset (por) v por 1.35 1.50 1.65 v figure 5.50, figure 5.51 voltage detection circuit (lvd0)* 1 v det0_0 3.67 3.84 3.97 v v det0_2 2.37 2.51 2.67 voltage detection circuit (lvd1)* 2 v det1_0 4.12 4.29 4.42 v figure 5.53 at falling edge vcc v det1_1 3.98 4.14 4.28 v det1_2 3.86 4.02 4.16 v det1_3 3.68 3.84 3.98 v det1_4 2.99 3.10 3.29 v det1_5 2.89 3.00 3.19 v det1_6 2.79 2.90 3.09 v det1_7 2.68 2.79 2.98 v det1_8 2.57 2.68 2.87 voltage detection circuit (lvd2)* 1 v det2_0 * 2 4.08 4.29 4.48 figure 5.54 at falling edge vcc v det2_1 3.95 4.14 4.35 v det2_2 3.82 4.02 4.22 v det2_3 3.62 3.84 4.02
r01ds0248ej0110 rev.1.10 page 82 of 98 jan 13, 2016 rx23t group 5. electrical characteristics note: these characteristics apply when noise is not superimposed on the power supply. wh en a setting is made so that the voltage detection level overlaps with that of the voltage detection circ uit (lvd1), it cannot be specified which of lvd1 and lvd2 is us ed for voltage detection. note 1. the minimum vcc down time indicates the time when vcc is below the minimum val ue of voltage detection levels v por , v det1 , and v det2 for the por/lvd. figure 5.50 voltage detection reset timing table 5.35 power-on reset circuit and volt age detection circuit characteristics (2) conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, ta = ?40 to +105c item symbol min. typ. max. unit test conditions wait time after power-on reset cancellation t por D 28.4 D ms figure 5.51 wait time after voltage monitoring 0 reset cancellation t lvd0 D 568 D s figure 5.52 wait time after voltage monitoring 1 reset cancellation t lvd1 D 100 D s figure 5.53 wait time after voltage monitoring 2 reset cancellation t lvd2 D 100 D s figure 5.54 response delay time t det DD 350 s figure 5.50 minimum vcc down time* 1 t voff 350 DD s figure 5.50, vcc = 1.0 v or above power-on reset enable time t w(por) 1 DD ms figure 5.51, vcc = below 1.0 v lvd operation stabilization time (after lvd is enabled) td (e-a) DD 300 s figure 5.53, figure 5.54 hysteresis width (lvd1 and lvd2) v lvh D 70 D mv vdet1_0 to 4 selected D 60 D vdet1_5 to 8, lvd2 selected internal reset signal (active-low) vcc t voff t por t det v por t det 1.0 v
r01ds0248ej0110 rev.1.10 page 83 of 98 jan 13, 2016 rx23t group 5. electrical characteristics figure 5.51 power-on reset timing figure 5.52 voltage detection circuit timing (vdet0) internal reset signal (active-low) vcc t por v por 1.0 v t w(por) *1 t det note 1. t w(por) is the time required for a power-on reset to be enabled while the external power vcc is being held below the valid voltage (1.0 v). when vcc turns on, maintain t w(por) for 1.0 ms or more. t voff v det0 vcc t det t det internal reset signal (active-low) v lvh t lvd0
r01ds0248ej0110 rev.1.10 page 84 of 98 jan 13, 2016 rx23t group 5. electrical characteristics figure 5.53 voltage detection circuit timing (v det1 ) figure 5.54 voltage detection circuit timing (v det2 ) t voff v det1 vcc t det t det t lvd1 t d(e-a) lvd1e lvd1 comparator output lvd1cmpe lvd1mon internal reset signal (active-low) when lvd1rn = l when lvd1rn = h v lvh t lvd1 t voff v det2 vcc t det t det t lvd2 t d(e-a) lvd2e lvd2 comparator output lvd2cmpe lvd2mon internal reset signal (active-low) when lvd2rn = l when lvd2rn = h v lvh t lvd2
r01ds0248ej0110 rev.1.10 page 85 of 98 jan 13, 2016 rx23t group 5. electrical characteristics 5.8 oscillation stop detection timing figure 5.55 oscillation stop detection timing table 5.36 oscillation stop detection timing conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, ta = ?40 to +105c item symbol min. typ. max. unit test conditions detection time t dr ? ? 1 ms figure 5.55 t dr main clock ostdsr.ostdf low-speed clock iclk t dr main clock ostdsr.ostdf iclk when the main clock is selected when the pll clock is selected pll clock
r01ds0248ej0110 rev.1.10 page 86 of 98 jan 13, 2016 rx23t group 5. electrical characteristics 5.9 rom (flash memory for code storage) characteristics note 1. definition of reprogram/erase cycle: the reprogram/erase cycle is the number of erasing for each block. when the reprogr am/ erase cycle is n times (n = 1000), erasing can be performed n times for each block. for instance, when 4-byte programming is performed 256 times for different addresses in 1-kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. however, programming the same address for se veral times as one erasing is not enabled (overwriting is prohibited). note 2. characteristic when using the flash memory programmer and the self-programming library provided from renesas electronics . note 3. this result is obtained from reliability testing. note: does not include the time until each operation of the flash me mory is started after instructions are executed by software. note: the lower-limit frequency of fclk is 1 mhz during programmi ng or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note: the frequency accuracy of fclk should be 3.5%. table 5.37 rom (flash memory for code storage) characteristics (1) item symbol min. typ. max. unit conditions reprogramming/erasure cycle* 1 n pec 1000 ? ? times data hold time after 1000 times of n pec t drp 20* 2, * 3 ? ? year t a = +85c table 5.38 rom (flash memory for code storage) characteristics (2): high-speed operating mode conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c temperature range for the programming/erasure operation: t a = ?40 to +85c item symbol fclk = 1 mhz fclk = 32 mhz unit min. typ. max. min. typ. max. programming time 8-byte t p8 ? 112.0 967.0 ? 52.3 490.5 s erasure time 2-kbyte t e2k ? 8.7 278.1 ? 5.5 214.6 ms 128-kbyte (when block erase command used) ? 239.7 5111.4 ? 25.9 734.3 ms 128-kbyte (when all- block erase command used) t e128k ? 234.5 4906.8 ? 20.6 524.6 ms blank check time 8-byte t bc8 ? ? 55.0 ? ? 16.1 s 2-kbyte t bc2k ? ? 1840.0 ? ? 135.7 s erase operation forcible stop time t sed ? ? 18.0 ? ? 10.7 s start-up area switching setting time t sas ? 12.3 566.5 ? 6.2 433.5 ms access window time t aws ? 12.3 566.5 ? 6.2 433.5 ms rom mode transition wait time 1 t dis 2.0 ? ? 2.0 ? ? s rom mode transition wait time 2 t ms 5.0 ? ? 5.0 ? ? s
r01ds0248ej0110 rev.1.10 page 87 of 98 jan 13, 2016 rx23t group 5. electrical characteristics note: does not include the time until each operation of the flash me mory is started after instructions are executed by software. note: the lower-limit frequency of fclk is 1 mhz during programmi ng or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note: the frequency accuracy of fclk should be 3.5%. table 5.39 rom (flash memory for code storage) characteristics (3): middle-speed operating mode conditions: vcc = 2.7 v to 5.5 v, avcc0 = vrefh0 = vcc to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c temperature range for the programming/erasure operation: t a = ?40 to +85c item symbol fclk = 1 mhz fclk = 8 mhz unit min. typ. max. min. typ. max. programming time 8-byte t p8 ? 152.0 1367.0 ? 97.9 936.0 s erasure time 2-kbyte t e2k ? 8.8 279.7 ? 5.9 220.8 ms 128-kbyte (when block erase command used) ? 239.8 5114.7 ? 55.5 1336.4 ms 128-kbyte (when all- block erase command used) t e128k ? 234.6 4908.5 ? 50.3 1130.1 ms blank check time 8-byte t bc8 ? ? 85.0 ? ? 50.9 s 2-kbyte t bc2k ? ? 1870.0 ? ? 401.5 s erase operation forcible stop time t sed ? ? 28.0 ? ? 21.3 s start-up area switching setting time t sas ? 13.0 573.3 ? 7.7 450.1 ms access window time t aws ? 13.0 573.3 ? 7.7 450.1 ms rom mode transition wait time 1 t dis 2.0 ? ? 2.0 ? ? s rom mode transition wait time 2 t ms 3.0 ? ? 3.0 ? ? s
r01ds0248ej0110 rev.1.10 page 88 of 98 jan 13, 2016 rx23t group 5. electrical characteristics 5.10 usage notes 5.10.1 connecting vcl capacitor and bypass capacitors this mcu integrates an internal voltage-down circuit, which is used for lowering the power supply voltage in the internal mcu to adjust automatically to the optimum level. a 4.7- f capacitor needs to be connected between this internal voltage-down power supply (vcl pin) and vss pin. figure 5.56 to figure 5.58 shows how to connect external capacitors. place an external capacitor close to the pins. do not apply th e power supply volta ge to the vcl pin. insert a multilayer ceramic capacitor as a bypass capacitor between each pair of the power supply pins. implement a bypass capacitor to the mcu power supply pins as close as possible. use a recommended value of 0.1 f as the capacitance of the capacitors. for the capacito rs related to crystal oscillation, see section 9, clock generation circuit in the user?s manual: hardware . for the capacitors related to analog modules, also see section 29, 12-bit a/d converter (s12ade) in the user?s manual: hardware . for notes on designing the printed circuit board, see the descriptions of the application note "hardware design guide" (r01an1411ej). the latest version can be do wnloaded from renesas electronics website.
r01ds0248ej0110 rev.1.10 page 89 of 98 jan 13, 2016 rx23t group 5. electrical characteristics figure 5.56 connecting capacitors (64 pins) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 54 55 51 49 50 52 53 56 57 58 59 60 61 63 64 62 rx23t group PLQP0064KB-C (64-pin lqfp) (top view) vss vcc vss vcc vcl vss vcc external capacitor for power supply stabilization 4.7 f bypass capacitor 0.1 f bypass capacitor 0.1 f bypass capacitor 0.1 f note 1. do not apply the power supply voltage to the vcl pin . note 2. use a 4.7-f multilayer ceramic for the vcl pin and place it close to the pin . a recommended value is shown for the capacitance of the bypass capacitors .
r01ds0248ej0110 rev.1.10 page 90 of 98 jan 13, 2016 rx23t group 5. electrical characteristics figure 5.57 connecting capacitors (52 pins) 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 45 46 42 40 41 43 44 47 48 49 50 51 52 rx23t group plqp0052ja-b (52-pin lqfp) (top view) vss vcc vcc vcl vss vcc 16 15 14 bypass capacitor 0.1 f external capacitor for power supply stabilization 4.7 f bypass capacitor 0.1 f bypass capacitor 0.1 f note 1. do not apply the power supply voltage to the vcl pin . note 2. use a 4.7-f multilayer ceramic for the vcl pin and place it close to the pin . a recommended value is shown for the capacitance of the bypass capacitors .
r01ds0248ej0110 rev.1.10 page 91 of 98 jan 13, 2016 rx23t group 5. electrical characteristics figure 5.58 connecting capacitors (48 pins) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12 38 39 37 40 41 42 43 44 45 47 48 46 rx23t group plqp0048kb-b (48-pin lqfp) (top view) vss vcc vcc vcl vss vcc 18 17 16 15 14 13 bypass capacitor 0.1 f bypass capacitor 0.1 f external capacitor for power supply stabilization 4.7 f bypass capacitor 0.1 f note 1. do not apply the power supply voltage to the vcl pin . note 2. use a 4.7-f multilayer ceramic for the vcl pin and place it close to the pin . a recommended value is shown for the capacitance of the bypass capacitors .
r01ds0248ej0110 rev.1.10 page 92 of 98 jan 13, 2016 rx23t group appendix 1. package dimensions appendix 1. package dimensions information on the latest version of the package dimensions or mountings has been displayed in ?packages? on renesas electronics corporation website. figure a 64-pin lf qfp (PLQP0064KB-C)
r01ds0248ej0110 rev.1.10 page 93 of 98 jan 13, 2016 rx23t group appendix 1. package dimensions figure b 52-pin lqfp (plqp0052ja-b)
r01ds0248ej0110 rev.1.10 page 94 of 98 jan 13, 2016 rx23t group appendix 1. package dimensions figure c 48 -pin lfqfp (plqp0048kb-b)
r01ds0248ej0110 rev.1.10 page 95 of 98 jan 13, 2016 rx23t group revision history classifications - items with technical update document number: changes according to the corresponding i ssued technical update - items without technical update documen t number: minor changes that do not re quire technical update to be issued revision history rx 23t group datasheet rev. date description classification page summary 1.00 mar 31, 2015 ? first edition, issued 1.10 oct 30, 2015 features 1 features changed 1. overview 2, 3 table 1.1 outline of specifications (1/3) (2/3) changed 6 table 1.3 list of products: d ve rsion (ta = ?40 to +85c) changed 6 table 1.4 list of products: g version (ta = ?40 to +105c) changed 7 figure 1.1 how to read the product part number changed 10 table 1.5 pin functions (2/2) changed 11 figure 1.3 pin assignments of the 64-pin lfqfp changed 12 figure 1.4 pin assignments of the 52-pin lqfp changed 13 figure 1.5 pin assignments of the 48-pin lfqfp changed 14 table 1.6 list of pins and pin f unctions (64-pin lfqfp) (1/2) changed 16 table 1.7 list of pins and pi n functions (52-pin lqfp) changed 17 table 1.8 list of pins and pi n functions (48-pin lfqfp) changed 3. address space 22 figure 3.1 memory map in each operating mode changed 4. i/o registers 25 table 4.1 list of i/o registers (address order) (1 / 16) address: 0008 0036h high-speed on-chip oscillator control register (hococr), address: 0008 00a5h high-speed on-chip oscillator wait control register (hocowtcr) added 34 table 4.1 list of i/o registers (address order) (10 / 16) address: 0008 c087h open drain control register 1 (odr1) added 5. electrical characteristics 42 table 5.3 dc characteristics (1) changed 57 table 5.14 operating frequency value (high-speed operating mode), table 5.15 operating frequency value (middle-speed operating mode) changed 58 table 5.16 clock timing, figure 5.20 extal external clock input timing changed 59, 60 figure 5.24 hoco clock oscillati on start timing (after reset is canceled by setting ofs1.hocoen bit to 0), fi gure 5.25 hoco cl ock oscillation start timing (oscillation is star ted by setting hococr.hcstp bit) added 79 table 5.32 comparator characteristics changed 80 table 5.33 d/a conversion characteristics symbol added 82 table 5.35 power-on reset circ uit and voltage detection circuit characteristics (2) changed 83 figure 5.52 voltage detection circuit timing (vdet0) changed 89 figure 5.56 connecting capacitors (64 pins) changed 90 figure 5.57 connecting capacitors (52 pins) changed 91 figure 5.58 connecting capacitors (48 pins) changed appendix 1. package dimensions 92 figure a 64-pin lfqfp (PLQP0064KB-C) changed 93 figure b 52-pin lqfp (plqp0052ja-b) changed 94 figure c 48 -pin lfqfp (plqp0048kb-b) changed revision history
notes for cmos devices (1) voltage application waveform at input pin: waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between vil (max) and vih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cm os device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an in ternal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resist or if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) precaution against esd: a strong electric fi eld, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade t he device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequat e. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be gr ounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touc hed with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not necessarily define the in itial status of a mos device. immediately after the power source is turn ed on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o setti ngs or contents of registers. a device is not initialized un til the reset signal is received. a re set operation must be executed immediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the po wer supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that re sults from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal cu rrent that passes in the device at this time may cause degradation of internal elem ents. input of signals during th e power off state must be judged separately for each device and according to re lated specifications governing the device.
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu pr oducts from renesas. for detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are generally in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromag netic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal be come possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applie d to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset pr ocess is completed. in a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provid ed for the possible future expansi on of functions. do not access these addresses; the correct operation of ls i is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program ex ecution, wait until the target clock signal has stabilized. ? when the clock signal is gene rated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only re leased after full stabilization of the clock signal. moreover, when switching to a clock signal produc ed with an external resonator (or by an external oscillator) while program ex ecution is in progress, wait until t he target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to a product with a different part number, confirm that the change will not lead to problems. ? the characteristics of an mpu or mcu in the same group but having a different part number may differ in terms of the internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, ope rating margins, immunity to noise, and amount of radiated noise. when changing to a product with a different part number, implement a system-evaluation test for the given product.
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"standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti-crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat t o human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. you should use the renesas electronics products described in this document within the range specified by renesas electronics, e specially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas e lectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have spec ific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatib ility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics products, who distributes, disposes of, or otherwis e places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of renesas e lectronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this documen t or renesas electronics products, or if you have any other inquiries. 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